vlsi1217

//
// This is a simple version of a 64 bit floating point multiplier 
// connected to a floating point adder. These are for
// use in EE287 as a homework problem, and later you will change it to 
// for higher performance.
// These are reduced complexity floating point.  There is no NaN
// overflow, underflow, or infinity values processed.
// The double precision is assumed to cover all possible signal
// processing requirements by the architects.
//

vlsi1217

//`define ntaps 43
`timescale 1ns/10ps
//`include "DW02_mult_2_stage.v"

module fir(clk,reset,flagin,din,dout,flagout);
input clk, flagin,reset;
input [31:0] din;
output signed [31:0] dout;
//input [5:0] waddr;
//input wstrobe;

vlsi1217

clear;close all;clc;
%% Talked to Grant today and I will make the all.csv into: "Fail or Zero"
%  for all tests, there is only Fail or not Fail, no summation of Failure
%  Then for all units, sum up the Fail conditions in terms of units number
N = csvread('P:\July2013\assignment\July12\goodData\sn604_MF_clean.csv');
M = zeros(size(N));
biasN = zeros(size(N));
for i = 2:3:size(N,1)
    for j = 2:size(N,2)
        biasN(i-1,j) = N(i-1,j);

vlsi1217

open(IN,"<E9N2D.3_Retest_7units_25C.txt");
open(OUT,">E9N2D.3_Retest_7units_25C_EXTRACTION.txt");
while(<IN>)
{
     chomp;
   if( $_ =~ m/\(F\)/ ){
		#if ($_ =~ m/Bin\:\s\s\d/){
        print OUT $_."\n" ;
		}
	  if( $_ =~ m/\(A\)/ ){

vlsi1217

import collections
import math
import random
import copy
import time

f = open('kargerMinCut.txt')
Gin={}
for each in f.readlines():
    each=map(int, each.split())

vlsi1217

clear;close all;clc;
%% LOOKOUT! for example, sn269 only have failure in 0.61 0.62 0.63 0.64 0.68 0.71 0.72 0.73
% test to extract features of failure report
% there are 13 voltages and 5 features
M = csvread('P:\July2013\assignment\July17\Anomal contributer data\sn36.csv');

%diff_vol = 13;
diff_vol = length(unique(M(2:end, 1)));
high_voltage = 61+diff_vol-1;

vlsi1217

%% draw boxplot and distribution for different lots in matlab
%  http://www.ics.uci.edu/~vpalepu/2013/03/03/Plotting-Box-plots-in-Groups-for-Vectors-of-Varying-Lengths.html
clear all;
close all;
clc;

% read data
[ndata, text, alldata] = ...
    xlsread('P:\July2013\assignment\July30\Try_SQL\1.xls');
[r,c] = size(text);

vlsi1217

www.pudn.com > ahb_master1.rar > ahb_master1.v, change:2008-12-08,size:5713b

    

module ahb_master(HBUSREQ,HLOCK,HTRANS,HADDR,HWRITE,HSIZE,HBURST,HWDATA,HSEL,hcount,HRESETn,HCLK,HGRANT,HREADY,HRESP,HRDATA,BUSREQ,ADDREQ,WRITE,ADDR,SIZE,BURST,SEL,TRANS,WDATA); 
 
output HBUSREQ,HLOCK,HWRITE; 
output [1:0]HTRANS,HSEL; 
output [31:0]HADDR,HWDATA; 
output [2:0]HSIZE,HBURST; 

vlsi1217

GUIDANCE
Add support for the Packet Receiver side
1. Declare a list for each port (data, valid, suspend) of type inout simple_port
2. Add a constraint to set the number of ports based on the list size
3. Create constraint with for each loop on list to connect
	Use implicit "index" to model DUT signal name

SYNTAX
Constraint size of list

vlsi1217

GUIDANCE
1. Instantiate signal map - name it smp
2. Print value of valid, data, suspend of ouput port 0
	by referencing signal map

SYNTAX
Do not randomize signal map unit
!map_instance_name: map_def_name_u;