test

// -----// IR Dump After mlir::iree_compiler::IREE::ABI::WrapEntryPointsPass (iree-abi-wrap-entry-points) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  func.func private @_split_reduction_pass2() {
    %0 = util.unfoldable_constant dense<1> : tensor<512x256x128xi32>
    %c0_i32 = arith.constant 0 : i32
    %1 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
    %2 = linalg.fill ins(%c0_i32 : i32) outs(%1 : tensor<512x256xi32>) -> tensor<512x256xi32>
    %3 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%0 : tensor<512x256x128xi32>) outs(%1 : tensor<512x256xi32>) {
    ^bb0(%arg0: i32, %arg1: i32):
      %4 = arith.addi %arg0, %arg1 : i32
      linalg.yield %4 : i32
    } -> tensor<512x256xi32>
    check.expect_eq_const(%3, dense<128> : tensor<512x256xi32>) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  func.func private @_split_reduction_pass2() {
    %cst = arith.constant dense<128> : tensor<512x256xi32>
    %cst_0 = arith.constant dense<1> : tensor<512x256x128xi32>
    %0 = util.do_not_optimize(%cst_0) : tensor<512x256x128xi32>
    %1 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
    %2 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%0 : tensor<512x256x128xi32>) outs(%1 : tensor<512x256xi32>) {
    ^bb0(%arg0: i32, %arg1: i32):
      %3 = arith.addi %arg0, %arg1 : i32
      linalg.yield %3 : i32
    } -> tensor<512x256xi32>
    check.expect_eq(%2, %cst) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Inliner (inline) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  func.func private @_split_reduction_pass2() {
    %cst = arith.constant dense<128> : tensor<512x256xi32>
    %cst_0 = arith.constant dense<1> : tensor<512x256x128xi32>
    %0 = util.do_not_optimize(%cst_0) : tensor<512x256x128xi32>
    %1 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
    %2 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%0 : tensor<512x256x128xi32>) outs(%1 : tensor<512x256xi32>) {
    ^bb0(%arg0: i32, %arg1: i32):
      %3 = arith.addi %arg0, %arg1 : i32
      linalg.yield %3 : i32
    } -> tensor<512x256xi32>
    check.expect_eq(%2, %cst) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After DispatchLinalgOnTensors (iree-flow-dispatch-linalg-on-tensors-pass) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  func.func private @_split_reduction_pass2() {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %cst = arith.constant dense<128> : tensor<512x256xi32>
    %cst_0 = arith.constant dense<1> : tensor<512x256x128xi32>
    %0 = util.do_not_optimize(%cst_0) : tensor<512x256x128xi32>
    %1 = flow.dispatch.workgroups[%c512, %c256, %c1](%0) : (tensor<512x256x128xi32>) -> tensor<512x256xi32> =
        (%arg0: !flow.dispatch.tensor<readonly:512x256x128xi32>, %arg1: !flow.dispatch.tensor<writeonly:512x256xi32>) {
      %2 = flow.dispatch.tensor.load %arg0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
      %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
      %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
      ^bb0(%arg2: i32, %arg3: i32):
        %5 = arith.addi %arg2, %arg3 : i32
        linalg.yield %5 : i32
      } -> tensor<512x256xi32>
      flow.dispatch.tensor.store %4, %arg1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
      flow.return
    } count(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      flow.return %x, %y, %z : index, index, index
    }
    check.expect_eq(%1, %cst) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After OutlineDispatchRegions (iree-flow-outline-dispatch-regions) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  flow.executable private @_split_reduction_pass2_dispatch_0 {
    flow.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !flow.dispatch.tensor<readonly:512x256x128xi32>, %arg1: !flow.dispatch.tensor<writeonly:512x256xi32>) {
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %1 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %2 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%0 : tensor<512x256x128xi32>) outs(%1 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %3 = arith.addi %arg2, %arg3 : i32
          linalg.yield %3 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %2, %arg1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %cst = arith.constant dense<128> : tensor<512x256xi32>
    %cst_0 = arith.constant dense<1> : tensor<512x256x128xi32>
    %0 = util.do_not_optimize(%cst_0) : tensor<512x256x128xi32>
    %1 = flow.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%0) : (tensor<512x256x128xi32>) -> tensor<512x256xi32>
    check.expect_eq(%1, %cst) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After ConvertToStream (iree-stream-conversion) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %cst = stream.tensor.constant : tensor<512x256xi32> in !stream.resource<constant> = dense<128> : tensor<512x256xi32>
    %0 = stream.resource.size %cst : !stream.resource<constant>
    %1 = stream.async.transfer %cst : !stream.resource<constant>{%0} -> !stream.resource<*>{%0}
    %cst_0 = stream.tensor.constant : tensor<512x256x128xi32> in !stream.resource<constant> = dense<1> : tensor<512x256x128xi32>
    %2 = stream.resource.size %cst_0 : !stream.resource<constant>
    %3 = stream.async.transfer %cst_0 : !stream.resource<constant>{%2} -> !stream.resource<*>{%2}
    %4 = util.do_not_optimize(%3) : !stream.resource<*>
    %5 = stream.resource.size %4 : !stream.resource<*>
    %6 = stream.tensor.sizeof tensor<512x256xi32> : index
    %7 = stream.async.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%4) : (!stream.resource<*>{%5}) -> !stream.resource<*>{%6}
    %8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
    %9 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%6} -> tensor<512x256xi32>
    %10 = stream.async.transfer %1 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
    %11 = stream.tensor.export %10 : tensor<512x256xi32> in !stream.resource<external>{%0} -> tensor<512x256xi32>
    check.expect_eq(%9, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.tensor.sizeof tensor<512x256xi32> : index
    %1 = stream.tensor.splat %c128_i32 : i32 -> tensor<512x256xi32> in !stream.resource<*>{%0}
    %2 = stream.tensor.sizeof tensor<512x256x128xi32> : index
    %3 = stream.tensor.splat %c1_i32 : i32 -> tensor<512x256x128xi32> in !stream.resource<*>{%2}
    %4 = util.do_not_optimize(%3) : !stream.resource<*>
    %5 = stream.resource.size %4 : !stream.resource<*>
    %6 = stream.tensor.sizeof tensor<512x256xi32> : index
    %7 = stream.async.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%4) : (!stream.resource<*>{%5}) -> !stream.resource<*>{%6}
    %8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
    %9 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%6} -> tensor<512x256xi32>
    %10 = stream.async.transfer %1 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
    %11 = stream.tensor.export %10 : tensor<512x256xi32> in !stream.resource<external>{%0} -> tensor<512x256xi32>
    check.expect_eq(%9, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After CSE (cse) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.tensor.sizeof tensor<512x256xi32> : index
    %1 = stream.tensor.splat %c128_i32 : i32 -> tensor<512x256xi32> in !stream.resource<*>{%0}
    %2 = stream.tensor.sizeof tensor<512x256x128xi32> : index
    %3 = stream.tensor.splat %c1_i32 : i32 -> tensor<512x256x128xi32> in !stream.resource<*>{%2}
    %4 = util.do_not_optimize(%3) : !stream.resource<*>
    %5 = stream.resource.size %4 : !stream.resource<*>
    %6 = stream.async.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%4) : (!stream.resource<*>{%5}) -> !stream.resource<*>{%0}
    %7 = stream.async.transfer %6 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
    %8 = stream.tensor.export %7 : tensor<512x256xi32> in !stream.resource<external>{%0} -> tensor<512x256xi32>
    %9 = stream.async.transfer %1 : !stream.resource<*>{%0} -> !stream.resource<external>{%0}
    %10 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%0} -> tensor<512x256xi32>
    check.expect_eq(%8, %10) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After EncodeHostTensors (iree-stream-encode-host-tensors) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.async.splat %c128_i32 : i32 -> !stream.resource<*>{%c524288}
    %1 = stream.async.splat %c1_i32 : i32 -> !stream.resource<*>{%c67108864}
    %2 = util.do_not_optimize(%1) : !stream.resource<*>
    %3 = stream.resource.size %2 : !stream.resource<*>
    %4 = stream.async.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%2) : (!stream.resource<*>{%3}) -> !stream.resource<*>{%c524288}
    %5 = stream.async.transfer %4 : !stream.resource<*>{%c524288} -> !stream.resource<external>{%c524288}
    %6 = stream.tensor.export %5 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %7 = stream.async.transfer %0 : !stream.resource<*>{%c524288} -> !stream.resource<external>{%c524288}
    %8 = stream.tensor.export %7 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%6, %8) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.async.splat %c1_i32 : i32 -> !stream.resource<*>{%c67108864}
    %1 = util.do_not_optimize(%0) : !stream.resource<*>
    %2 = stream.resource.size %1 : !stream.resource<*>
    %3 = stream.async.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%1) : (!stream.resource<*>{%2}) -> !stream.resource<*>{%c524288}
    %4 = stream.async.transfer %3 : !stream.resource<*>{%c524288} -> !stream.resource<external>{%c524288}
    %5 = stream.tensor.export %4 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %6 = stream.async.splat %c128_i32 : i32 -> !stream.resource<*>{%c524288}
    %7 = stream.async.transfer %6 : !stream.resource<*>{%c524288} -> !stream.resource<external>{%c524288}
    %8 = stream.tensor.export %7 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%5, %8) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After RefineUsage (iree-stream-refine-usage) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.async.splat %c1_i32 : i32 -> !stream.resource<transient>{%c67108864}
    %1 = util.do_not_optimize(%0) : !stream.resource<transient>
    %2 = stream.resource.size %1 : !stream.resource<transient>
    %3 = stream.async.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%1) : (!stream.resource<transient>{%2}) -> !stream.resource<external>{%c524288}
    %4 = stream.tensor.export %3 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %5 = stream.async.splat %c128_i32 : i32 -> !stream.resource<external>{%c524288}
    %6 = stream.tensor.export %5 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%4, %6) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After ScheduleExecution (iree-stream-schedule-execution) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %results, %result_timepoint = stream.async.execute with() -> !stream.resource<transient>{%c67108864} {
      %6 = stream.async.splat %c1_i32 : i32 -> !stream.resource<transient>{%c67108864}
      stream.yield %6 : !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %0 = stream.timepoint.await %result_timepoint => %results : !stream.resource<transient>{%c67108864}
    %1 = util.do_not_optimize(%0) : !stream.resource<transient>
    %2 = stream.resource.size %1 : !stream.resource<transient>
    %results_0:2, %result_timepoint_1 = stream.async.execute with(%1 as %arg0: !stream.resource<transient>{%2}) -> (!stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}) {
      %6 = stream.async.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%arg0) : (!stream.resource<transient>{%2}) -> !stream.resource<external>{%c524288}
      %7 = stream.async.splat %c128_i32 : i32 -> !stream.resource<external>{%c524288}
      stream.yield %6, %7 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    } => !stream.timepoint
    %3:2 = stream.timepoint.await %result_timepoint_1 => %results_0#0, %results_0#1 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    %4 = stream.tensor.export %3#0 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %5 = stream.tensor.export %3#1 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%4, %5) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After ScheduleConcurrency (iree-stream-schedule-concurrency) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %results, %result_timepoint = stream.async.execute with() -> !stream.resource<transient>{%c67108864} {
      %6 = stream.async.splat %c1_i32 : i32 -> !stream.resource<transient>{%c67108864}
      stream.yield %6 : !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %0 = stream.timepoint.await %result_timepoint => %results : !stream.resource<transient>{%c67108864}
    %1 = util.do_not_optimize(%0) : !stream.resource<transient>
    %2 = stream.resource.size %1 : !stream.resource<transient>
    %results_0:2, %result_timepoint_1 = stream.async.execute with(%1 as %arg0: !stream.resource<transient>{%2}) -> (!stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}) {
      %6:2 = stream.async.concurrent with(%arg0 as %arg1: !stream.resource<transient>{%2}) -> (!stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}) {
        %7 = stream.async.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%arg1) : (!stream.resource<transient>{%2}) -> !stream.resource<external>{%c524288}
        %8 = stream.async.splat %c128_i32 : i32 -> !stream.resource<external>{%c524288}
        stream.yield %7, %8 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
      }
      stream.yield %6#0, %6#1 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    } => !stream.timepoint
    %3:2 = stream.timepoint.await %result_timepoint_1 => %results_0#0, %results_0#1 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    %4 = stream.tensor.export %3#0 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %5 = stream.tensor.export %3#1 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%4, %5) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After PropagateTimepoints (iree-stream-propagate-timepoints) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %results, %result_timepoint = stream.async.execute with() -> !stream.resource<transient>{%c67108864} {
      %8 = stream.async.splat %c1_i32 : i32 -> !stream.resource<transient>{%c67108864}
      stream.yield %8 : !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %0 = stream.timepoint.await %result_timepoint => %results : !stream.resource<transient>{%c67108864}
    %1 = util.do_not_optimize(%0) : !stream.resource<transient>
    %2 = stream.resource.size %1 : !stream.resource<transient>
    %3 = stream.timepoint.immediate => !stream.timepoint
    %4 = stream.timepoint.immediate => !stream.timepoint
    %results_0:2, %result_timepoint_1 = stream.async.execute await(%4) => with(%1 as %arg0: !stream.resource<transient>{%2}) -> (!stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}) {
      %8:2 = stream.async.concurrent with(%arg0 as %arg1: !stream.resource<transient>{%2}) -> (!stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}) {
        %9 = stream.async.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%arg1) : (!stream.resource<transient>{%2}) -> !stream.resource<external>{%c524288}
        %10 = stream.async.splat %c128_i32 : i32 -> !stream.resource<external>{%c524288}
        stream.yield %9, %10 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
      }
      stream.yield %8#0, %8#1 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    } => !stream.timepoint
    %5:2 = stream.timepoint.await %result_timepoint_1 => %results_0#0, %results_0#1 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    %6 = stream.tensor.export %5#0 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %7 = stream.tensor.export %5#1 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%6, %7) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %results, %result_timepoint = stream.async.execute with() -> !stream.resource<transient>{%c67108864} {
      %6 = stream.async.splat %c1_i32 : i32 -> !stream.resource<transient>{%c67108864}
      stream.yield %6 : !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %0 = stream.timepoint.await %result_timepoint => %results : !stream.resource<transient>{%c67108864}
    %1 = util.do_not_optimize(%0) : !stream.resource<transient>
    %2 = stream.resource.size %1 : !stream.resource<transient>
    %results_0:2, %result_timepoint_1 = stream.async.execute with(%1 as %arg0: !stream.resource<transient>{%2}) -> (!stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}) {
      %6:2 = stream.async.concurrent with(%arg0 as %arg1: !stream.resource<transient>{%2}) -> (!stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}) {
        %7 = stream.async.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%arg1) : (!stream.resource<transient>{%2}) -> !stream.resource<external>{%c524288}
        %8 = stream.async.splat %c128_i32 : i32 -> !stream.resource<external>{%c524288}
        stream.yield %7, %8 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
      }
      stream.yield %6#0, %6#1 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    } => !stream.timepoint
    %3:2 = stream.timepoint.await %result_timepoint_1 => %results_0#0, %results_0#1 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    %4 = stream.tensor.export %3#0 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %5 = stream.tensor.export %3#1 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%4, %5) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After ScheduleAllocation (iree-stream-schedule-allocation) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %c0 = arith.constant 0 : index
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %c0_0 = arith.constant 0 : index
    %5:2 = stream.resource.alloc uninitialized : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5#0 as %arg1: !stream.resource<external>{%c524288}, %5#1 as %arg2: !stream.resource<external>{%c524288}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0_0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0_0 for %c524288] : !stream.resource<external>{%c524288}
        }
        stream.cmd.fill %c128_i32, %arg2[%c0_0 for %c524288] : i32 -> !stream.resource<external>{%c524288}
      }
    } => !stream.timepoint
    %7:2 = stream.timepoint.await %6 => %5#0, %5#1 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    %8 = stream.tensor.export %7#0 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %9 = stream.tensor.export %7#1 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%8, %9) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After PackAllocations (iree-stream-pack-allocations) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %c0 = arith.constant 0 : index
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %c0_0 = arith.constant 0 : index
    %5:3 = stream.resource.pack slices({
      [0, 0] = %c524288,
      [0, 0] = %c524288
    }) : index
    %6 = stream.resource.alloc uninitialized : !stream.resource<external>{%5#0}
    %7 = stream.resource.subview %6[%5#1] : !stream.resource<external>{%5#0} -> !stream.resource<external>{%c524288}
    %8 = stream.resource.subview %6[%5#2] : !stream.resource<external>{%5#0} -> !stream.resource<external>{%c524288}
    %9 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %7 as %arg1: !stream.resource<external>{%c524288}, %8 as %arg2: !stream.resource<external>{%c524288}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0_0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0_0 for %c524288] : !stream.resource<external>{%c524288}
        }
        stream.cmd.fill %c128_i32, %arg2[%c0_0 for %c524288] : i32 -> !stream.resource<external>{%c524288}
      }
    } => !stream.timepoint
    %10:2 = stream.timepoint.await %9 => %7, %8 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    %11 = stream.tensor.export %10#0 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %12 = stream.tensor.export %10#1 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%11, %12) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LayoutSlices (iree-stream-layout-slices) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %c0 = arith.constant 0 : index
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %c0_0 = arith.constant 0 : index
    %c0_1 = arith.constant 0 : index
    %c524288_2 = arith.constant 524288 : index
    %c524288_3 = arith.constant 524288 : index
    %c1048576 = arith.constant 1048576 : index
    %c1048576_4 = arith.constant 1048576 : index
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576_4}
    %6 = stream.resource.subview %5[%c0_1] : !stream.resource<external>{%c1048576_4} -> !stream.resource<external>{%c524288}
    %7 = stream.resource.subview %5[%c524288_3] : !stream.resource<external>{%c1048576_4} -> !stream.resource<external>{%c524288}
    %8 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %6 as %arg1: !stream.resource<external>{%c524288}, %7 as %arg2: !stream.resource<external>{%c524288}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0_0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0_0 for %c524288] : !stream.resource<external>{%c524288}
        }
        stream.cmd.fill %c128_i32, %arg2[%c0_0 for %c524288] : i32 -> !stream.resource<external>{%c524288}
      }
    } => !stream.timepoint
    %9:2 = stream.timepoint.await %8 => %6, %7 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %9#0 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9#1 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After PropagateSubranges (iree-util-propagate-subranges) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %c0_0 = arith.constant 0 : index
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0_0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %c0_1 = arith.constant 0 : index
    %c0_2 = arith.constant 0 : index
    %c524288_3 = arith.constant 524288 : index
    %c524288_4 = arith.constant 524288 : index
    %c1048576 = arith.constant 1048576 : index
    %c1048576_5 = arith.constant 1048576 : index
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576_5}
    %6 = stream.resource.subview %5[%c0_2] : !stream.resource<external>{%c1048576_5} -> !stream.resource<external>{%c524288}
    %7 = stream.resource.subview %5[%c524288_4] : !stream.resource<external>{%c1048576_5} -> !stream.resource<external>{%c524288}
    %8 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %6 as %arg1: !stream.resource<external>{%c524288}, %7 as %arg2: !stream.resource<external>{%c524288}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0_1 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0_1 for %c524288] : !stream.resource<external>{%c524288}
        }
        stream.cmd.fill %c128_i32, %arg2[%c0_1 for %c524288] : i32 -> !stream.resource<external>{%c524288}
      }
    } => !stream.timepoint
    %9:2 = stream.timepoint.await %8 => %6, %7 : !stream.resource<external>{%c524288}, !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %9#0 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9#1 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c524288] : !stream.resource<external>{%c1048576}
        }
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After FuseDispatchBindings (iree-stream-fuse-dispatch-bindings) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: index, %arg3: index) {
        %c0 = arith.constant 0 : index
        %0 = arith.addi %c0, %arg2 : index
        %1 = stream.binding.subspan %arg0[%0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %2 = arith.addi %c0, %arg3 : index
        %3 = stream.binding.subspan %arg1[%2] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %5 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %6 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%4 : tensor<512x256x128xi32>) outs(%5 : tensor<512x256xi32>) {
        ^bb0(%arg4: i32, %arg5: i32):
          %7 = arith.addi %arg4, %arg5 : i32
          linalg.yield %7 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %6, %3, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %c0_0 = arith.constant 0 : index
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%c0, %c0 : index, index) {
          ro %arg0[%c0_0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0_0 for %c1048576] : !stream.resource<external>{%c1048576}
        }
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After PackDispatchOperands (iree-stream-pack-dispatch-operands) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: i32, %arg3: i32) {
        %0 = arith.index_cast %arg2 : i32 to index
        %1 = arith.index_cast %arg3 : i32 to index
        %c0 = arith.constant 0 : index
        %2 = arith.addi %c0, %0 : index
        %3 = stream.binding.subspan %arg0[%2] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %4 = arith.addi %c0, %1 : index
        %5 = stream.binding.subspan %arg1[%4] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %6 = flow.dispatch.tensor.load %3, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %7 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %8 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%6 : tensor<512x256x128xi32>) outs(%7 : tensor<512x256xi32>) {
        ^bb0(%arg4: i32, %arg5: i32):
          %9 = arith.addi %arg4, %arg5 : i32
          linalg.yield %9 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %8, %5, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %c0_0 = arith.constant 0 : index
    %c0_i32 = arith.constant 0 : i32
    %c0_i32_1 = arith.constant 0 : i32
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%c0_i32, %c0_i32_1 : i32, i32) {
          ro %arg0[%c0_0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0_0 for %c1048576] : !stream.resource<external>{%c1048576}
        }
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After CSE (cse) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: i32, %arg3: i32) {
        %0 = arith.index_cast %arg2 : i32 to index
        %1 = arith.index_cast %arg3 : i32 to index
        %c0 = arith.constant 0 : index
        %2 = arith.addi %c0, %0 : index
        %3 = stream.binding.subspan %arg0[%2] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %4 = arith.addi %c0, %1 : index
        %5 = stream.binding.subspan %arg1[%4] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %6 = flow.dispatch.tensor.load %3, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %7 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %8 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%6 : tensor<512x256x128xi32>) outs(%7 : tensor<512x256xi32>) {
        ^bb0(%arg4: i32, %arg5: i32):
          %9 = arith.addi %arg4, %arg5 : i32
          linalg.yield %9 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %8, %5, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %c0_i32 = arith.constant 0 : i32
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1](%c0_i32, %c0_i32 : i32, i32) {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        }
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After FoldUniformOperands (iree-stream-fold-uniform-operands) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding, %arg1: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %0 = arith.index_cast %c0_i32 : i32 to index
        %1 = arith.index_cast %c0_i32 : i32 to index
        %c0 = arith.constant 0 : index
        %2 = arith.addi %c0, %0 : index
        %3 = stream.binding.subspan %arg0[%2] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %4 = arith.addi %c0, %1 : index
        %5 = stream.binding.subspan %arg1[%4] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %6 = flow.dispatch.tensor.load %3, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %7 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %8 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%6 : tensor<512x256x128xi32>) outs(%7 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %9 = arith.addi %arg2, %arg3 : i32
          linalg.yield %9 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %8, %5, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %c0_i32 = arith.constant 0 : i32
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        }
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After AnnotateDispatchArguments (iree-stream-annotate-dispatch-arguments) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %0 = arith.index_cast %c0_i32 : i32 to index
        %1 = arith.index_cast %c0_i32 : i32 to index
        %c0 = arith.constant 0 : index
        %2 = arith.addi %c0, %0 : index
        %3 = stream.binding.subspan %arg0[%2] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %4 = arith.addi %c0, %1 : index
        %5 = stream.binding.subspan %arg1[%4] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %6 = flow.dispatch.tensor.load %3, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %7 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %8 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%6 : tensor<512x256x128xi32>) outs(%7 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %9 = arith.addi %arg2, %arg3 : i32
          linalg.yield %9 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %8, %5, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %c0_i32 = arith.constant 0 : i32
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        }
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('func.func' operation: @_split_reduction_pass2) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %0 = arith.index_cast %c0_i32 : i32 to index
        %1 = arith.index_cast %c0_i32 : i32 to index
        %c0 = arith.constant 0 : index
        %2 = arith.addi %c0, %0 : index
        %3 = stream.binding.subspan %arg0[%2] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %4 = arith.addi %c0, %1 : index
        %5 = stream.binding.subspan %arg1[%4] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %6 = flow.dispatch.tensor.load %3, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %7 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %8 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%6 : tensor<512x256x128xi32>) outs(%7 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %9 = arith.addi %arg2, %arg3 : i32
          linalg.yield %9 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %8, %5, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        }
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After ApplyPatterns (iree-util-apply-patterns) ('builtin.module' operation) //----- //
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        }
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::AssignTargetDevicesPass (iree-hal-assign-target-devices) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  stream.executable private @_split_reduction_pass2_dispatch_0 {
    stream.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 workgroups(%arg0: index, %arg1: index, %arg2: index) -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg0, %arg1, %arg2
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:512x256x128xi32>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:512x256xi32>
        %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
        %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
        %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
        ^bb0(%arg2: i32, %arg3: i32):
          %5 = arith.addi %arg2, %arg3 : i32
          linalg.yield %5 : i32
        } -> tensor<512x256xi32>
        flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
        return
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        }
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::(anonymous namespace)::MaterializeInterfacesPass (iree-hal-materialize-interfaces) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg1, %arg2, %arg3
        hal.return %x, %y, %z : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %2 = flow.dispatch.tensor.load %0, offsets = [0, 0, 0], sizes = [512, 256, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<512x256x128xi32>
          %3 = linalg.init_tensor [512, 256] : tensor<512x256xi32>
          %4 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "reduction"]} ins(%2 : tensor<512x256x128xi32>) outs(%3 : tensor<512x256xi32>) {
          ^bb0(%arg0: i32, %arg1: i32):
            %5 = arith.addi %arg0, %arg1 : i32
            linalg.yield %5 : i32
          } -> tensor<512x256xi32>
          flow.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [512, 256], strides = [1, 1] : tensor<512x256xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After TileAndDistributeToWorkgroups (iree-codegen-tile-and-distribute-to-workgroups) ('hal.executable.variant' operation: @embedded_elf_x86_64) //----- //
#config = #iree_codegen.lowering_config<tile_sizes = [[32, 32, 0], [1, 4, 0], [0, 0, 4]]>
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map0()[%workgroup_id_y]
          %3 = affine.apply #map0()[%workgroup_count_y]
          scf.for %arg0 = %2 to %c512 step %3 {
            %4 = affine.apply #map0()[%workgroup_id_x]
            %5 = affine.apply #map0()[%workgroup_count_x]
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [%c32, %c32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<?x?x128xi32>
              %7 = linalg.init_tensor [32, 32] : tensor<32x32xi32>
              %8 = tensor.cast %6 : tensor<?x?x128xi32> to tensor<32x32x128xi32>
              %9 = linalg.generic {indexing_maps = [#map1, #map2], iterator_types = ["parallel", "parallel", "reduction"]} ins(%8 : tensor<32x32x128xi32>) outs(%7 : tensor<32x32xi32>) attrs =  {lowering_config = #config} {
              ^bb0(%arg2: i32, %arg3: i32):
                %11 = arith.addi %arg2, %arg3 : i32
                linalg.yield %11 : i32
              } -> tensor<32x32xi32>
              %10 = tensor.cast %9 : tensor<32x32xi32> to tensor<?x?xi32>
              flow.dispatch.tensor.store %10, %1, offsets = [%arg0, %arg1], sizes = [%c32, %c32], strides = [1, 1] : tensor<?x?xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After ConvertToDestinationPassingStyle (iree-codegen-convert-to-destination-passing-style) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#config = #iree_codegen.lowering_config<tile_sizes = [[32, 32, 0], [1, 4, 0], [0, 0, 4]]>
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map0()[%workgroup_id_y]
          %3 = affine.apply #map0()[%workgroup_count_y]
          scf.for %arg0 = %2 to %c512 step %3 {
            %4 = affine.apply #map0()[%workgroup_id_x]
            %5 = affine.apply #map0()[%workgroup_count_x]
            scf.for %arg1 = %4 to %c256 step %5 {
              %c32_0 = arith.constant 32 : index
              %6 = flow.dispatch.tensor.load %1, offsets = [%arg0, %arg1], sizes = [%c32_0, %c32_0], strides = [1, 1] : !flow.dispatch.tensor<writeonly:512x256xi32> -> tensor<?x?xi32>
              %7 = tensor.cast %6 : tensor<?x?xi32> to tensor<32x32xi32>
              %8 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [%c32, %c32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<?x?x128xi32>
              %9 = linalg.init_tensor [32, 32] : tensor<32x32xi32>
              %10 = tensor.cast %8 : tensor<?x?x128xi32> to tensor<32x32x128xi32>
              %11 = linalg.generic {indexing_maps = [#map1, #map2], iterator_types = ["parallel", "parallel", "reduction"]} ins(%10 : tensor<32x32x128xi32>) outs(%7 : tensor<32x32xi32>) attrs =  {lowering_config = #config} {
              ^bb0(%arg2: i32, %arg3: i32):
                %13 = arith.addi %arg2, %arg3 : i32
                linalg.yield %13 : i32
              } -> tensor<32x32xi32>
              %12 = tensor.cast %11 : tensor<32x32xi32> to tensor<?x?xi32>
              flow.dispatch.tensor.store %12, %1, offsets = [%arg0, %arg1], sizes = [%c32, %c32], strides = [1, 1] : tensor<?x?xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After FoldAffineMinInDistributedLoops (iree-codegen-fold-affinemin-in-distributed-loops) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#config = #iree_codegen.lowering_config<tile_sizes = [[32, 32, 0], [1, 4, 0], [0, 0, 4]]>
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map0()[%workgroup_id_y]
          %3 = affine.apply #map0()[%workgroup_count_y]
          scf.for %arg0 = %2 to %c512 step %3 {
            %4 = affine.apply #map0()[%workgroup_id_x]
            %5 = affine.apply #map0()[%workgroup_count_x]
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = flow.dispatch.tensor.load %1, offsets = [%arg0, %arg1], sizes = [%c32, %c32], strides = [1, 1] : !flow.dispatch.tensor<writeonly:512x256xi32> -> tensor<?x?xi32>
              %7 = tensor.cast %6 : tensor<?x?xi32> to tensor<32x32xi32>
              %8 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [%c32, %c32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<?x?x128xi32>
              %9 = tensor.cast %8 : tensor<?x?x128xi32> to tensor<32x32x128xi32>
              %10 = linalg.generic {indexing_maps = [#map1, #map2], iterator_types = ["parallel", "parallel", "reduction"]} ins(%9 : tensor<32x32x128xi32>) outs(%7 : tensor<32x32xi32>) attrs =  {lowering_config = #config} {
              ^bb0(%arg2: i32, %arg3: i32):
                %12 = arith.addi %arg2, %arg3 : i32
                linalg.yield %12 : i32
              } -> tensor<32x32xi32>
              %11 = tensor.cast %10 : tensor<32x32xi32> to tensor<?x?xi32>
              flow.dispatch.tensor.store %11, %1, offsets = [%arg0, %arg1], sizes = [%c32, %c32], strides = [1, 1] : tensor<?x?xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('builtin.module' operation) //----- //
#config = #iree_codegen.lowering_config<tile_sizes = [[32, 32, 0], [1, 4, 0], [0, 0, 4]]>
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map0()[%workgroup_id_y]
          %3 = affine.apply #map0()[%workgroup_count_y]
          scf.for %arg0 = %2 to %c512 step %3 {
            %4 = affine.apply #map0()[%workgroup_id_x]
            %5 = affine.apply #map0()[%workgroup_count_x]
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = flow.dispatch.tensor.load %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : !flow.dispatch.tensor<writeonly:512x256xi32> -> tensor<32x32xi32>
              %7 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [32, 32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<32x32x128xi32>
              %8 = linalg.generic {indexing_maps = [#map1, #map2], iterator_types = ["parallel", "parallel", "reduction"]} ins(%7 : tensor<32x32x128xi32>) outs(%6 : tensor<32x32xi32>) attrs =  {lowering_config = #config} {
              ^bb0(%arg2: i32, %arg3: i32):
                %9 = arith.addi %arg2, %arg3 : i32
                linalg.yield %9 : i32
              } -> tensor<32x32xi32>
              flow.dispatch.tensor.store %8, %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : tensor<32x32xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgStrategyTileAndFusePass (iree-linalg-strategy-tile-and-fuse-pass) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#config = #iree_codegen.lowering_config<tile_sizes = [[32, 32, 0], [1, 4, 0], [0, 0, 4]]>
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map0()[%workgroup_id_y]
          %3 = affine.apply #map0()[%workgroup_count_y]
          scf.for %arg0 = %2 to %c512 step %3 {
            %4 = affine.apply #map0()[%workgroup_id_x]
            %5 = affine.apply #map0()[%workgroup_count_x]
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = flow.dispatch.tensor.load %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : !flow.dispatch.tensor<writeonly:512x256xi32> -> tensor<32x32xi32>
              %7 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [32, 32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<32x32x128xi32>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %6) -> (tensor<32x32xi32>) {
                %9 = scf.for %arg4 = %c0 to %c32 step %c4 iter_args(%arg5 = %arg3) -> (tensor<32x32xi32>) {
                  %10 = tensor.extract_slice %7[%arg2, %arg4, 0] [1, 4, 128] [1, 1, 1] : tensor<32x32x128xi32> to tensor<1x4x128xi32>
                  %11 = tensor.extract_slice %arg5[%arg2, %arg4] [1, 4] [1, 1] : tensor<32x32xi32> to tensor<1x4xi32>
                  %12 = linalg.generic {indexing_maps = [#map1, #map2], iterator_types = ["parallel", "parallel", "reduction"]} ins(%10 : tensor<1x4x128xi32>) outs(%11 : tensor<1x4xi32>) attrs =  {__internal_linalg_transform__ = "1", lowering_config = #config} {
                  ^bb0(%arg6: i32, %arg7: i32):
                    %14 = arith.addi %arg6, %arg7 : i32
                    linalg.yield %14 : i32
                  } -> tensor<1x4xi32>
                  %13 = tensor.insert_slice %12 into %arg5[%arg2, %arg4] [1, 4] [1, 1] : tensor<1x4xi32> into tensor<32x32xi32>
                  scf.yield %13 : tensor<32x32xi32>
                }
                scf.yield %9 : tensor<32x32xi32>
              }
              flow.dispatch.tensor.store %8, %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : tensor<32x32xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgStrategyRemoveMarkersPass (iree-linalg-strategy-remove-markers-pass) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#config = #iree_codegen.lowering_config<tile_sizes = [[32, 32, 0], [1, 4, 0], [0, 0, 4]]>
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map0()[%workgroup_id_y]
          %3 = affine.apply #map0()[%workgroup_count_y]
          %4 = affine.apply #map0()[%workgroup_id_x]
          %5 = affine.apply #map0()[%workgroup_count_x]
          scf.for %arg0 = %2 to %c512 step %3 {
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = flow.dispatch.tensor.load %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : !flow.dispatch.tensor<writeonly:512x256xi32> -> tensor<32x32xi32>
              %7 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [32, 32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<32x32x128xi32>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %6) -> (tensor<32x32xi32>) {
                %9 = scf.for %arg4 = %c0 to %c32 step %c4 iter_args(%arg5 = %arg3) -> (tensor<32x32xi32>) {
                  %10 = tensor.extract_slice %7[%arg2, %arg4, 0] [1, 4, 128] [1, 1, 1] : tensor<32x32x128xi32> to tensor<1x4x128xi32>
                  %11 = tensor.extract_slice %arg5[%arg2, %arg4] [1, 4] [1, 1] : tensor<32x32xi32> to tensor<1x4xi32>
                  %12 = linalg.generic {indexing_maps = [#map1, #map2], iterator_types = ["parallel", "parallel", "reduction"]} ins(%10 : tensor<1x4x128xi32>) outs(%11 : tensor<1x4xi32>) attrs =  {lowering_config = #config} {
                  ^bb0(%arg6: i32, %arg7: i32):
                    %14 = arith.addi %arg6, %arg7 : i32
                    linalg.yield %14 : i32
                  } -> tensor<1x4xi32>
                  %13 = tensor.insert_slice %12 into %arg5[%arg2, %arg4] [1, 4] [1, 1] : tensor<1x4xi32> into tensor<32x32xi32>
                  scf.yield %13 : tensor<32x32xi32>
                }
                scf.yield %9 : tensor<32x32xi32>
              }
              flow.dispatch.tensor.store %8, %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : tensor<32x32xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgFuse (linalg-fuse) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#config = #iree_codegen.lowering_config<tile_sizes = [[32, 32, 0], [1, 4, 0], [0, 0, 4]]>
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map0()[%workgroup_id_y]
          %3 = affine.apply #map0()[%workgroup_count_y]
          %4 = affine.apply #map0()[%workgroup_id_x]
          %5 = affine.apply #map0()[%workgroup_count_x]
          scf.for %arg0 = %2 to %c512 step %3 {
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = flow.dispatch.tensor.load %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : !flow.dispatch.tensor<writeonly:512x256xi32> -> tensor<32x32xi32>
              %7 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [32, 32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<32x32x128xi32>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %6) -> (tensor<32x32xi32>) {
                %9 = scf.for %arg4 = %c0 to %c32 step %c4 iter_args(%arg5 = %arg3) -> (tensor<32x32xi32>) {
                  %10 = tensor.extract_slice %7[%arg2, %arg4, 0] [1, 4, 128] [1, 1, 1] : tensor<32x32x128xi32> to tensor<1x4x128xi32>
                  %11 = tensor.extract_slice %arg5[%arg2, %arg4] [1, 4] [1, 1] : tensor<32x32xi32> to tensor<1x4xi32>
                  %12 = linalg.generic {indexing_maps = [#map1, #map2], iterator_types = ["parallel", "parallel", "reduction"]} ins(%10 : tensor<1x4x128xi32>) outs(%11 : tensor<1x4xi32>) attrs =  {lowering_config = #config} {
                  ^bb0(%arg6: i32, %arg7: i32):
                    %14 = arith.addi %arg6, %arg7 : i32
                    linalg.yield %14 : i32
                  } -> tensor<1x4xi32>
                  %13 = tensor.insert_slice %12 into %arg5[%arg2, %arg4] [1, 4] [1, 1] : tensor<1x4xi32> into tensor<32x32xi32>
                  scf.yield %13 : tensor<32x32xi32>
                }
                scf.yield %9 : tensor<32x32xi32>
              }
              flow.dispatch.tensor.store %8, %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : tensor<32x32xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgSplitReduction (linalg-split-reduction) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
#map2 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
#map3 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
#map4 = affine_map<(d0, d1, d2) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map0()[%workgroup_id_y]
          %3 = affine.apply #map0()[%workgroup_count_y]
          %4 = affine.apply #map0()[%workgroup_id_x]
          %5 = affine.apply #map0()[%workgroup_count_x]
          scf.for %arg0 = %2 to %c512 step %3 {
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = flow.dispatch.tensor.load %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : !flow.dispatch.tensor<writeonly:512x256xi32> -> tensor<32x32xi32>
              %7 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [32, 32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<32x32x128xi32>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %6) -> (tensor<32x32xi32>) {
                %9 = scf.for %arg4 = %c0 to %c32 step %c4 iter_args(%arg5 = %arg3) -> (tensor<32x32xi32>) {
                  %10 = tensor.extract_slice %7[%arg2, %arg4, 0] [1, 4, 128] [1, 1, 1] : tensor<32x32x128xi32> to tensor<1x4x128xi32>
                  %11 = tensor.extract_slice %arg5[%arg2, %arg4] [1, 4] [1, 1] : tensor<32x32xi32> to tensor<1x4xi32>
                  %12 = tensor.expand_shape %10 [[0], [1], [2, 3]] : tensor<1x4x128xi32> into tensor<1x4x32x4xi32>
                  %13 = linalg.init_tensor [1, 4, 4] : tensor<1x4x4xi32>
                  %14 = linalg.fill ins(%c0_i32 : i32) outs(%13 : tensor<1x4x4xi32>) -> tensor<1x4x4xi32>
                  %15 = scf.for %arg6 = %c0 to %c32 step %c1 iter_args(%arg7 = %14) -> (tensor<1x4x4xi32>) {
                    %18 = tensor.extract_slice %12[0, 0, %arg6, 0] [1, 4, 1, 4] [1, 1, 1, 1] : tensor<1x4x32x4xi32> to tensor<1x4x1x4xi32>
                    %19 = linalg.generic {indexing_maps = [#map1, #map2], iterator_types = ["parallel", "parallel", "reduction", "parallel"]} ins(%18 : tensor<1x4x1x4xi32>) outs(%arg7 : tensor<1x4x4xi32>) {
                    ^bb0(%arg8: i32, %arg9: i32):
                      %20 = arith.addi %arg8, %arg9 : i32
                      linalg.yield %20 : i32
                    } -> tensor<1x4x4xi32>
                    scf.yield %19 : tensor<1x4x4xi32>
                  }
                  %16 = linalg.generic {indexing_maps = [#map3, #map4], iterator_types = ["parallel", "parallel", "reduction"]} ins(%15 : tensor<1x4x4xi32>) outs(%11 : tensor<1x4xi32>) {
                  ^bb0(%arg6: i32, %arg7: i32):
                    %18 = arith.addi %arg6, %arg7 : i32
                    linalg.yield %18 : i32
                  } -> tensor<1x4xi32>
                  %17 = tensor.insert_slice %16 into %arg5[%arg2, %arg4] [1, 4] [1, 1] : tensor<1x4xi32> into tensor<32x32xi32>
                  scf.yield %17 : tensor<32x32xi32>
                }
                scf.yield %9 : tensor<32x32xi32>
              }
              flow.dispatch.tensor.store %8, %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : tensor<32x32xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgStrategyVectorizePass (iree-linalg-strategy-vectorize-pass) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_count_y]
          %4 = affine.apply #map()[%workgroup_id_x]
          %5 = affine.apply #map()[%workgroup_count_x]
          scf.for %arg0 = %2 to %c512 step %3 {
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = flow.dispatch.tensor.load %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : !flow.dispatch.tensor<writeonly:512x256xi32> -> tensor<32x32xi32>
              %7 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [32, 32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<32x32x128xi32>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %6) -> (tensor<32x32xi32>) {
                %9 = scf.for %arg4 = %c0 to %c32 step %c4 iter_args(%arg5 = %arg3) -> (tensor<32x32xi32>) {
                  %10 = tensor.extract_slice %7[%arg2, %arg4, 0] [1, 4, 128] [1, 1, 1] : tensor<32x32x128xi32> to tensor<1x4x128xi32>
                  %11 = tensor.expand_shape %10 [[0], [1], [2, 3]] : tensor<1x4x128xi32> into tensor<1x4x32x4xi32>
                  %12 = linalg.init_tensor [1, 4, 4] : tensor<1x4x4xi32>
                  %13 = vector.transfer_write %cst, %12[%c0, %c0, %c0] {in_bounds = [true, true, true]} : vector<1x4x4xi32>, tensor<1x4x4xi32>
                  %14 = scf.for %arg6 = %c0 to %c32 step %c1 iter_args(%arg7 = %13) -> (tensor<1x4x4xi32>) {
                    %19 = vector.transfer_read %11[%c0, %c0, %arg6, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : tensor<1x4x32x4xi32>, vector<1x4x1x4xi32>
                    %20 = vector.transfer_read %arg7[%c0, %c0, %c0], %c0_i32 {in_bounds = [true, true, true]} : tensor<1x4x4xi32>, vector<1x4x4xi32>
                    %21 = vector.multi_reduction <add>, %19, %20 [2] : vector<1x4x1x4xi32> to vector<1x4x4xi32>
                    %22 = vector.transfer_write %21, %arg7[%c0, %c0, %c0] {in_bounds = [true, true, true]} : vector<1x4x4xi32>, tensor<1x4x4xi32>
                    scf.yield %22 : tensor<1x4x4xi32>
                  }
                  %15 = vector.transfer_read %14[%c0, %c0, %c0], %c0_i32 {in_bounds = [true, true, true]} : tensor<1x4x4xi32>, vector<1x4x4xi32>
                  %16 = vector.transfer_read %arg5[%arg2, %arg4], %c0_i32 {in_bounds = [true, true]} : tensor<32x32xi32>, vector<1x4xi32>
                  %17 = vector.multi_reduction <add>, %15, %16 [2] : vector<1x4x4xi32> to vector<1x4xi32>
                  %18 = vector.transfer_write %17, %arg5[%arg2, %arg4] {in_bounds = [true, true]} : vector<1x4xi32>, tensor<32x32xi32>
                  scf.yield %18 : tensor<32x32xi32>
                }
                scf.yield %9 : tensor<32x32xi32>
              }
              flow.dispatch.tensor.store %8, %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : tensor<32x32xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgStrategyEnablePass (iree-linalg-strategy-enable-pass) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_count_y]
          %4 = affine.apply #map()[%workgroup_id_x]
          %5 = affine.apply #map()[%workgroup_count_x]
          scf.for %arg0 = %2 to %c512 step %3 {
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = flow.dispatch.tensor.load %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : !flow.dispatch.tensor<writeonly:512x256xi32> -> tensor<32x32xi32>
              %7 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [32, 32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<32x32x128xi32>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %6) -> (tensor<32x32xi32>) {
                %9 = scf.for %arg4 = %c0 to %c32 step %c4 iter_args(%arg5 = %arg3) -> (tensor<32x32xi32>) {
                  %10 = tensor.extract_slice %7[%arg2, %arg4, 0] [1, 4, 128] [1, 1, 1] : tensor<32x32x128xi32> to tensor<1x4x128xi32>
                  %11 = tensor.expand_shape %10 [[0], [1], [2, 3]] : tensor<1x4x128xi32> into tensor<1x4x32x4xi32>
                  %12 = scf.for %arg6 = %c0 to %c32 step %c1 iter_args(%arg7 = %cst) -> (vector<1x4x4xi32>) {
                    %16 = vector.transfer_read %11[%c0, %c0, %arg6, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : tensor<1x4x32x4xi32>, vector<1x4x1x4xi32>
                    %17 = vector.multi_reduction <add>, %16, %arg7 [2] : vector<1x4x1x4xi32> to vector<1x4x4xi32>
                    scf.yield %17 : vector<1x4x4xi32>
                  }
                  %13 = vector.transfer_read %arg5[%arg2, %arg4], %c0_i32 {in_bounds = [true, true]} : tensor<32x32xi32>, vector<1x4xi32>
                  %14 = vector.multi_reduction <add>, %12, %13 [2] : vector<1x4x4xi32> to vector<1x4xi32>
                  %15 = vector.transfer_write %14, %arg5[%arg2, %arg4] {in_bounds = [true, true]} : vector<1x4xi32>, tensor<32x32xi32>
                  scf.yield %15 : tensor<32x32xi32>
                }
                scf.yield %9 : tensor<32x32xi32>
              }
              flow.dispatch.tensor.store %8, %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : tensor<32x32xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgSingleTilingExpert (linalg-single-tiling-expert-driver) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_count_y]
          %4 = affine.apply #map()[%workgroup_id_x]
          %5 = affine.apply #map()[%workgroup_count_x]
          scf.for %arg0 = %2 to %c512 step %3 {
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = flow.dispatch.tensor.load %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : !flow.dispatch.tensor<writeonly:512x256xi32> -> tensor<32x32xi32>
              %7 = flow.dispatch.tensor.load %0, offsets = [%arg0, %arg1, 0], sizes = [32, 32, 128], strides = [1, 1, 1] : !flow.dispatch.tensor<readonly:512x256x128xi32> -> tensor<32x32x128xi32>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %6) -> (tensor<32x32xi32>) {
                %9 = scf.for %arg4 = %c0 to %c32 step %c4 iter_args(%arg5 = %arg3) -> (tensor<32x32xi32>) {
                  %10 = tensor.extract_slice %7[%arg2, %arg4, 0] [1, 4, 128] [1, 1, 1] : tensor<32x32x128xi32> to tensor<1x4x128xi32>
                  %11 = tensor.expand_shape %10 [[0], [1], [2, 3]] : tensor<1x4x128xi32> into tensor<1x4x32x4xi32>
                  %12 = scf.for %arg6 = %c0 to %c32 step %c1 iter_args(%arg7 = %cst) -> (vector<1x4x4xi32>) {
                    %16 = vector.transfer_read %11[%c0, %c0, %arg6, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : tensor<1x4x32x4xi32>, vector<1x4x1x4xi32>
                    %17 = vector.multi_reduction <add>, %16, %arg7 [2] : vector<1x4x1x4xi32> to vector<1x4x4xi32>
                    scf.yield %17 : vector<1x4x4xi32>
                  }
                  %13 = vector.transfer_read %arg5[%arg2, %arg4], %c0_i32 {in_bounds = [true, true]} : tensor<32x32xi32>, vector<1x4xi32>
                  %14 = vector.multi_reduction <add>, %12, %13 [2] : vector<1x4x4xi32> to vector<1x4xi32>
                  %15 = vector.transfer_write %14, %arg5[%arg2, %arg4] {in_bounds = [true, true]} : vector<1x4xi32>, tensor<32x32xi32>
                  scf.yield %15 : tensor<32x32xi32>
                }
                scf.yield %9 : tensor<32x32xi32>
              }
              flow.dispatch.tensor.store %8, %1, offsets = [%arg0, %arg1], sizes = [32, 32], strides = [1, 1] : tensor<32x32xi32> -> !flow.dispatch.tensor<writeonly:512x256xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After IREEComprehensiveBufferize (iree-codegen-iree-comprehensive-bufferize) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %2 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %2, 64 : memref<512x256xi32>
          %3 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %4 = affine.apply #map0()[%workgroup_id_y]
          %5 = affine.apply #map0()[%workgroup_count_y]
          %6 = affine.apply #map0()[%workgroup_id_x]
          %7 = affine.apply #map0()[%workgroup_count_x]
          scf.for %arg0 = %4 to %c512 step %5 {
            scf.for %arg1 = %6 to %c256 step %7 {
              %8 = memref.subview %2[%arg0, %arg1] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
              %9 = bufferization.to_tensor %8 : memref<32x32xi32, strided<[256, 1], offset: ?>>
              %10 = memref.subview %0[%arg0, %arg1, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
              %11 = bufferization.to_tensor %10 : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
              %12 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %8) -> (memref<32x32xi32, strided<[256, 1], offset: ?>>) {
                %15 = bufferization.to_tensor %arg3 : memref<32x32xi32, strided<[256, 1], offset: ?>>
                %16 = scf.for %arg4 = %c0 to %c32 step %c4 iter_args(%arg5 = %arg3) -> (memref<32x32xi32, strided<[256, 1], offset: ?>>) {
                  %18 = bufferization.to_tensor %arg5 : memref<32x32xi32, strided<[256, 1], offset: ?>>
                  %19 = memref.subview %10[%arg2, %arg4, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
                  %20 = bufferization.to_tensor %19 : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
                  %21 = memref.expand_shape %19 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
                  %22 = bufferization.to_tensor %21 : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
                  %23 = scf.for %arg6 = %c0 to %c32 step %c1 iter_args(%arg7 = %cst) -> (vector<1x4x4xi32>) {
                    %27 = vector.transfer_read %21[%c0, %c0, %arg6, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<1x4x1x4xi32>
                    %28 = vector.multi_reduction <add>, %27, %arg7 [2] : vector<1x4x1x4xi32> to vector<1x4x4xi32>
                    scf.yield %28 : vector<1x4x4xi32>
                  }
                  %24 = vector.transfer_read %arg5[%arg2, %arg4], %c0_i32 {in_bounds = [true, true]} : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<1x4xi32>
                  %25 = vector.multi_reduction <add>, %23, %24 [2] : vector<1x4x4xi32> to vector<1x4xi32>
                  vector.transfer_write %25, %arg5[%arg2, %arg4] {in_bounds = [true, true]} : vector<1x4xi32>, memref<32x32xi32, strided<[256, 1], offset: ?>>
                  %26 = bufferization.to_tensor %arg5 : memref<32x32xi32, strided<[256, 1], offset: ?>>
                  scf.yield %arg5 : memref<32x32xi32, strided<[256, 1], offset: ?>>
                }
                %17 = bufferization.to_tensor %16 : memref<32x32xi32, strided<[256, 1], offset: ?>>
                scf.yield %16 : memref<32x32xi32, strided<[256, 1], offset: ?>>
              }
              %13 = bufferization.to_tensor %12 : memref<32x32xi32, strided<[256, 1], offset: ?>>
              %14 = memref.subview %2[%arg0, %arg1] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
              linalg.generic {indexing_maps = [#map1, #map1], iterator_types = ["parallel", "parallel"]} ins(%12 : memref<32x32xi32, strided<[256, 1], offset: ?>>) outs(%14 : memref<32x32xi32, strided<[256, 1], offset: ?>>) {
              ^bb0(%arg2: i32, %arg3: i32):
                linalg.yield %arg2 : i32
              }
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After ResolveShapedTypeResultDims (resolve-shaped-type-result-dims) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %2 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %2, 64 : memref<512x256xi32>
          %3 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %4 = affine.apply #map0()[%workgroup_id_y]
          %5 = affine.apply #map0()[%workgroup_count_y]
          %6 = affine.apply #map0()[%workgroup_id_x]
          %7 = affine.apply #map0()[%workgroup_count_x]
          scf.for %arg0 = %4 to %c512 step %5 {
            scf.for %arg1 = %6 to %c256 step %7 {
              %8 = memref.subview %2[%arg0, %arg1] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
              %9 = memref.subview %0[%arg0, %arg1, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
              %10 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %8) -> (memref<32x32xi32, strided<[256, 1], offset: ?>>) {
                %12 = scf.for %arg4 = %c0 to %c32 step %c4 iter_args(%arg5 = %arg3) -> (memref<32x32xi32, strided<[256, 1], offset: ?>>) {
                  %13 = memref.subview %9[%arg2, %arg4, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
                  %14 = memref.expand_shape %13 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
                  %15 = scf.for %arg6 = %c0 to %c32 step %c1 iter_args(%arg7 = %cst) -> (vector<1x4x4xi32>) {
                    %18 = vector.transfer_read %14[%c0, %c0, %arg6, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<1x4x1x4xi32>
                    %19 = vector.multi_reduction <add>, %18, %arg7 [2] : vector<1x4x1x4xi32> to vector<1x4x4xi32>
                    scf.yield %19 : vector<1x4x4xi32>
                  }
                  %16 = vector.transfer_read %arg5[%arg2, %arg4], %c0_i32 {in_bounds = [true, true]} : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<1x4xi32>
                  %17 = vector.multi_reduction <add>, %15, %16 [2] : vector<1x4x4xi32> to vector<1x4xi32>
                  vector.transfer_write %17, %arg5[%arg2, %arg4] {in_bounds = [true, true]} : vector<1x4xi32>, memref<32x32xi32, strided<[256, 1], offset: ?>>
                  scf.yield %arg5 : memref<32x32xi32, strided<[256, 1], offset: ?>>
                }
                scf.yield %12 : memref<32x32xi32, strided<[256, 1], offset: ?>>
              }
              %11 = memref.subview %2[%arg0, %arg1] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
              linalg.generic {indexing_maps = [#map1, #map1], iterator_types = ["parallel", "parallel"]} ins(%10 : memref<32x32xi32, strided<[256, 1], offset: ?>>) outs(%11 : memref<32x32xi32, strided<[256, 1], offset: ?>>) {
              ^bb0(%arg2: i32, %arg3: i32):
                linalg.yield %arg2 : i32
              }
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %2 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %2, 64 : memref<512x256xi32>
          %3 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %4 = affine.apply #map0()[%workgroup_id_y]
          %5 = affine.apply #map0()[%workgroup_count_y]
          %6 = affine.apply #map0()[%workgroup_id_x]
          %7 = affine.apply #map0()[%workgroup_count_x]
          scf.for %arg0 = %4 to %c512 step %5 {
            scf.for %arg1 = %6 to %c256 step %7 {
              %8 = memref.subview %2[%arg0, %arg1] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
              %9 = memref.subview %0[%arg0, %arg1, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
              scf.for %arg2 = %c0 to %c32 step %c1 {
                scf.for %arg3 = %c0 to %c32 step %c4 {
                  %11 = memref.subview %9[%arg2, %arg3, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
                  %12 = memref.expand_shape %11 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
                  %13 = scf.for %arg4 = %c0 to %c32 step %c1 iter_args(%arg5 = %cst) -> (vector<1x4x4xi32>) {
                    %16 = vector.transfer_read %12[%c0, %c0, %arg4, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<1x4x1x4xi32>
                    %17 = vector.multi_reduction <add>, %16, %arg5 [2] : vector<1x4x1x4xi32> to vector<1x4x4xi32>
                    scf.yield %17 : vector<1x4x4xi32>
                  }
                  %14 = vector.transfer_read %8[%arg2, %arg3], %c0_i32 {in_bounds = [true, true]} : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<1x4xi32>
                  %15 = vector.multi_reduction <add>, %13, %14 [2] : vector<1x4x4xi32> to vector<1x4xi32>
                  vector.transfer_write %15, %8[%arg2, %arg3] {in_bounds = [true, true]} : vector<1x4xi32>, memref<32x32xi32, strided<[256, 1], offset: ?>>
                }
              }
              %10 = memref.subview %2[%arg0, %arg1] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
              linalg.generic {indexing_maps = [#map1, #map1], iterator_types = ["parallel", "parallel"]} ins(%8 : memref<32x32xi32, strided<[256, 1], offset: ?>>) outs(%10 : memref<32x32xi32, strided<[256, 1], offset: ?>>) {
              ^bb0(%arg2: i32, %arg3: i32):
                linalg.yield %arg2 : i32
              }
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After CSE (cse) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map0 = affine_map<()[s0] -> (s0 * 32)>
#map1 = affine_map<(d0, d1) -> (d0, d1)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %2 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %2, 64 : memref<512x256xi32>
          %3 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %4 = affine.apply #map0()[%workgroup_id_y]
          %5 = affine.apply #map0()[%workgroup_count_y]
          %6 = affine.apply #map0()[%workgroup_id_x]
          %7 = affine.apply #map0()[%workgroup_count_x]
          scf.for %arg0 = %4 to %c512 step %5 {
            scf.for %arg1 = %6 to %c256 step %7 {
              %8 = memref.subview %2[%arg0, %arg1] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
              %9 = memref.subview %0[%arg0, %arg1, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
              scf.for %arg2 = %c0 to %c32 step %c1 {
                scf.for %arg3 = %c0 to %c32 step %c4 {
                  %10 = memref.subview %9[%arg2, %arg3, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
                  %11 = memref.expand_shape %10 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
                  %12 = scf.for %arg4 = %c0 to %c32 step %c1 iter_args(%arg5 = %cst) -> (vector<1x4x4xi32>) {
                    %15 = vector.transfer_read %11[%c0, %c0, %arg4, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<1x4x1x4xi32>
                    %16 = vector.multi_reduction <add>, %15, %arg5 [2] : vector<1x4x1x4xi32> to vector<1x4x4xi32>
                    scf.yield %16 : vector<1x4x4xi32>
                  }
                  %13 = vector.transfer_read %8[%arg2, %arg3], %c0_i32 {in_bounds = [true, true]} : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<1x4xi32>
                  %14 = vector.multi_reduction <add>, %12, %13 [2] : vector<1x4x4xi32> to vector<1x4xi32>
                  vector.transfer_write %14, %8[%arg2, %arg3] {in_bounds = [true, true]} : vector<1x4xi32>, memref<32x32xi32, strided<[256, 1], offset: ?>>
                }
              }
              linalg.generic {indexing_maps = [#map1, #map1], iterator_types = ["parallel", "parallel"]} ins(%8 : memref<32x32xi32, strided<[256, 1], offset: ?>>) outs(%8 : memref<32x32xi32, strided<[256, 1], offset: ?>>) {
              ^bb0(%arg2: i32, %arg3: i32):
                linalg.yield %arg2 : i32
              }
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<readonly:512x256x128xi32>
          %2 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %2, 64 : memref<512x256xi32>
          %3 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : !flow.dispatch.tensor<writeonly:512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %4 = affine.apply #map()[%workgroup_id_y]
          %5 = affine.apply #map()[%workgroup_count_y]
          %6 = affine.apply #map()[%workgroup_id_x]
          %7 = affine.apply #map()[%workgroup_count_x]
          scf.for %arg0 = %4 to %c512 step %5 {
            scf.for %arg1 = %6 to %c256 step %7 {
              %8 = memref.subview %2[%arg0, %arg1] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
              %9 = memref.subview %0[%arg0, %arg1, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
              scf.for %arg2 = %c0 to %c32 step %c1 {
                scf.for %arg3 = %c0 to %c32 step %c4 {
                  %10 = memref.subview %9[%arg2, %arg3, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
                  %11 = memref.expand_shape %10 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
                  %12 = scf.for %arg4 = %c0 to %c32 step %c1 iter_args(%arg5 = %cst) -> (vector<1x4x4xi32>) {
                    %15 = vector.transfer_read %11[%c0, %c0, %arg4, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<1x4x1x4xi32>
                    %16 = vector.multi_reduction <add>, %15, %arg5 [2] : vector<1x4x1x4xi32> to vector<1x4x4xi32>
                    scf.yield %16 : vector<1x4x4xi32>
                  }
                  %13 = vector.transfer_read %8[%arg2, %arg3], %c0_i32 {in_bounds = [true, true]} : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<1x4xi32>
                  %14 = vector.multi_reduction <add>, %12, %13 [2] : vector<1x4x4xi32> to vector<1x4xi32>
                  vector.transfer_write %14, %8[%arg2, %arg3] {in_bounds = [true, true]} : vector<1x4xi32>, memref<32x32xi32, strided<[256, 1], offset: ?>>
                }
              }
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After CleanupBufferAllocView (iree-codegen-cleanup-buffer-alloc-view) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c512 = arith.constant 512 : index
          %c256 = arith.constant 256 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_count_x = hal.interface.workgroup.count[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %workgroup_count_y = hal.interface.workgroup.count[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_count_y]
          %4 = affine.apply #map()[%workgroup_id_x]
          %5 = affine.apply #map()[%workgroup_count_x]
          scf.for %arg0 = %2 to %c512 step %3 {
            scf.for %arg1 = %4 to %c256 step %5 {
              %6 = memref.subview %1[%arg0, %arg1] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
              %7 = memref.subview %0[%arg0, %arg1, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
              scf.for %arg2 = %c0 to %c32 step %c1 {
                scf.for %arg3 = %c0 to %c32 step %c4 {
                  %8 = memref.subview %7[%arg2, %arg3, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
                  %9 = memref.expand_shape %8 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
                  %10 = scf.for %arg4 = %c0 to %c32 step %c1 iter_args(%arg5 = %cst) -> (vector<1x4x4xi32>) {
                    %13 = vector.transfer_read %9[%c0, %c0, %arg4, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<1x4x1x4xi32>
                    %14 = vector.multi_reduction <add>, %13, %arg5 [2] : vector<1x4x1x4xi32> to vector<1x4x4xi32>
                    scf.yield %14 : vector<1x4x4xi32>
                  }
                  %11 = vector.transfer_read %6[%arg2, %arg3], %c0_i32 {in_bounds = [true, true]} : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<1x4xi32>
                  %12 = vector.multi_reduction <add>, %10, %11 [2] : vector<1x4x4xi32> to vector<1x4xi32>
                  vector.transfer_write %12, %6[%arg2, %arg3] {in_bounds = [true, true]} : vector<1x4xi32>, memref<32x32xi32, strided<[256, 1], offset: ?>>
                }
              }
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After RemoveSingleIterationLoop (iree-codegen-remove-single-iteration-loop) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          scf.for %arg0 = %c0 to %c32 step %c1 {
            scf.for %arg1 = %c0 to %c32 step %c4 {
              %6 = memref.subview %5[%arg0, %arg1, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
              %7 = memref.expand_shape %6 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %cst) -> (vector<1x4x4xi32>) {
                %11 = vector.transfer_read %7[%c0, %c0, %arg2, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<1x4x1x4xi32>
                %12 = vector.multi_reduction <add>, %11, %arg3 [2] : vector<1x4x1x4xi32> to vector<1x4x4xi32>
                scf.yield %12 : vector<1x4x4xi32>
              }
              %9 = vector.transfer_read %4[%arg0, %arg1], %c0_i32 {in_bounds = [true, true]} : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<1x4xi32>
              %10 = vector.multi_reduction <add>, %8, %9 [2] : vector<1x4x4xi32> to vector<1x4xi32>
              vector.transfer_write %10, %4[%arg0, %arg1] {in_bounds = [true, true]} : vector<1x4xi32>, memref<32x32xi32, strided<[256, 1], offset: ?>>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgStrategyLowerVectorsPass (iree-linalg-strategy-lower-vectors-pass) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<16xi32>
          %c5 = arith.constant 5 : index
          %c6 = arith.constant 6 : index
          %c7 = arith.constant 7 : index
          %c8 = arith.constant 8 : index
          %c9 = arith.constant 9 : index
          %c10 = arith.constant 10 : index
          %c11 = arith.constant 11 : index
          %c12 = arith.constant 12 : index
          %c13 = arith.constant 13 : index
          %c14 = arith.constant 14 : index
          %c15 = arith.constant 15 : index
          %cst_0 = arith.constant dense<0> : vector<4xi32>
          %c2 = arith.constant 2 : index
          %c3 = arith.constant 3 : index
          %cst_1 = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          scf.for %arg0 = %c0 to %c32 step %c1 {
            scf.for %arg1 = %c0 to %c32 step %c4 {
              %6 = memref.subview %5[%arg0, %arg1, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
              %7 = memref.expand_shape %6 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %cst_1) -> (vector<1x4x4xi32>) {
                %27 = vector.transfer_read %7[%c0, %c0, %arg2, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<1x4x1x4xi32>
                %28 = vector.transpose %27, [0, 1, 3, 2] : vector<1x4x1x4xi32> to vector<1x4x4x1xi32>
                %29 = vector.extract %28[0, 0, 0] : vector<1x4x4x1xi32>
                %30 = vector.extract %arg3[0, 0, 0] : vector<1x4x4xi32>
                %31 = vector.reduction <add>, %29, %30 : vector<1xi32> into i32
                %32 = vector.insertelement %31, %cst[%c0 : index] : vector<16xi32>
                %33 = vector.extract %28[0, 0, 1] : vector<1x4x4x1xi32>
                %34 = vector.extract %arg3[0, 0, 1] : vector<1x4x4xi32>
                %35 = vector.reduction <add>, %33, %34 : vector<1xi32> into i32
                %36 = vector.insertelement %35, %32[%c1 : index] : vector<16xi32>
                %37 = vector.extract %28[0, 0, 2] : vector<1x4x4x1xi32>
                %38 = vector.extract %arg3[0, 0, 2] : vector<1x4x4xi32>
                %39 = vector.reduction <add>, %37, %38 : vector<1xi32> into i32
                %40 = vector.insertelement %39, %36[%c2 : index] : vector<16xi32>
                %41 = vector.extract %28[0, 0, 3] : vector<1x4x4x1xi32>
                %42 = vector.extract %arg3[0, 0, 3] : vector<1x4x4xi32>
                %43 = vector.reduction <add>, %41, %42 : vector<1xi32> into i32
                %44 = vector.insertelement %43, %40[%c3 : index] : vector<16xi32>
                %45 = vector.extract %28[0, 1, 0] : vector<1x4x4x1xi32>
                %46 = vector.extract %arg3[0, 1, 0] : vector<1x4x4xi32>
                %47 = vector.reduction <add>, %45, %46 : vector<1xi32> into i32
                %48 = vector.insertelement %47, %44[%c4 : index] : vector<16xi32>
                %49 = vector.extract %28[0, 1, 1] : vector<1x4x4x1xi32>
                %50 = vector.extract %arg3[0, 1, 1] : vector<1x4x4xi32>
                %51 = vector.reduction <add>, %49, %50 : vector<1xi32> into i32
                %52 = vector.insertelement %51, %48[%c5 : index] : vector<16xi32>
                %53 = vector.extract %28[0, 1, 2] : vector<1x4x4x1xi32>
                %54 = vector.extract %arg3[0, 1, 2] : vector<1x4x4xi32>
                %55 = vector.reduction <add>, %53, %54 : vector<1xi32> into i32
                %56 = vector.insertelement %55, %52[%c6 : index] : vector<16xi32>
                %57 = vector.extract %28[0, 1, 3] : vector<1x4x4x1xi32>
                %58 = vector.extract %arg3[0, 1, 3] : vector<1x4x4xi32>
                %59 = vector.reduction <add>, %57, %58 : vector<1xi32> into i32
                %60 = vector.insertelement %59, %56[%c7 : index] : vector<16xi32>
                %61 = vector.extract %28[0, 2, 0] : vector<1x4x4x1xi32>
                %62 = vector.extract %arg3[0, 2, 0] : vector<1x4x4xi32>
                %63 = vector.reduction <add>, %61, %62 : vector<1xi32> into i32
                %64 = vector.insertelement %63, %60[%c8 : index] : vector<16xi32>
                %65 = vector.extract %28[0, 2, 1] : vector<1x4x4x1xi32>
                %66 = vector.extract %arg3[0, 2, 1] : vector<1x4x4xi32>
                %67 = vector.reduction <add>, %65, %66 : vector<1xi32> into i32
                %68 = vector.insertelement %67, %64[%c9 : index] : vector<16xi32>
                %69 = vector.extract %28[0, 2, 2] : vector<1x4x4x1xi32>
                %70 = vector.extract %arg3[0, 2, 2] : vector<1x4x4xi32>
                %71 = vector.reduction <add>, %69, %70 : vector<1xi32> into i32
                %72 = vector.insertelement %71, %68[%c10 : index] : vector<16xi32>
                %73 = vector.extract %28[0, 2, 3] : vector<1x4x4x1xi32>
                %74 = vector.extract %arg3[0, 2, 3] : vector<1x4x4xi32>
                %75 = vector.reduction <add>, %73, %74 : vector<1xi32> into i32
                %76 = vector.insertelement %75, %72[%c11 : index] : vector<16xi32>
                %77 = vector.extract %28[0, 3, 0] : vector<1x4x4x1xi32>
                %78 = vector.extract %arg3[0, 3, 0] : vector<1x4x4xi32>
                %79 = vector.reduction <add>, %77, %78 : vector<1xi32> into i32
                %80 = vector.insertelement %79, %76[%c12 : index] : vector<16xi32>
                %81 = vector.extract %28[0, 3, 1] : vector<1x4x4x1xi32>
                %82 = vector.extract %arg3[0, 3, 1] : vector<1x4x4xi32>
                %83 = vector.reduction <add>, %81, %82 : vector<1xi32> into i32
                %84 = vector.insertelement %83, %80[%c13 : index] : vector<16xi32>
                %85 = vector.extract %28[0, 3, 2] : vector<1x4x4x1xi32>
                %86 = vector.extract %arg3[0, 3, 2] : vector<1x4x4xi32>
                %87 = vector.reduction <add>, %85, %86 : vector<1xi32> into i32
                %88 = vector.insertelement %87, %84[%c14 : index] : vector<16xi32>
                %89 = vector.extract %28[0, 3, 3] : vector<1x4x4x1xi32>
                %90 = vector.extract %arg3[0, 3, 3] : vector<1x4x4xi32>
                %91 = vector.reduction <add>, %89, %90 : vector<1xi32> into i32
                %92 = vector.insertelement %91, %88[%c15 : index] : vector<16xi32>
                %93 = vector.shape_cast %92 : vector<16xi32> to vector<1x4x4xi32>
                scf.yield %93 : vector<1x4x4xi32>
              }
              %9 = vector.transfer_read %4[%arg0, %arg1], %c0_i32 {in_bounds = [true, true]} : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<1x4xi32>
              %10 = vector.extract %8[0, 0] : vector<1x4x4xi32>
              %11 = vector.extract %9[0, 0] : vector<1x4xi32>
              %12 = vector.reduction <add>, %10, %11 : vector<4xi32> into i32
              %13 = vector.insertelement %12, %cst_0[%c0 : index] : vector<4xi32>
              %14 = vector.extract %8[0, 1] : vector<1x4x4xi32>
              %15 = vector.extract %9[0, 1] : vector<1x4xi32>
              %16 = vector.reduction <add>, %14, %15 : vector<4xi32> into i32
              %17 = vector.insertelement %16, %13[%c1 : index] : vector<4xi32>
              %18 = vector.extract %8[0, 2] : vector<1x4x4xi32>
              %19 = vector.extract %9[0, 2] : vector<1x4xi32>
              %20 = vector.reduction <add>, %18, %19 : vector<4xi32> into i32
              %21 = vector.insertelement %20, %17[%c2 : index] : vector<4xi32>
              %22 = vector.extract %8[0, 3] : vector<1x4x4xi32>
              %23 = vector.extract %9[0, 3] : vector<1x4xi32>
              %24 = vector.reduction <add>, %22, %23 : vector<4xi32> into i32
              %25 = vector.insertelement %24, %21[%c3 : index] : vector<4xi32>
              %26 = vector.shape_cast %25 : vector<4xi32> to vector<1x4xi32>
              vector.transfer_write %26, %4[%arg0, %arg1] {in_bounds = [true, true]} : vector<1x4xi32>, memref<32x32xi32, strided<[256, 1], offset: ?>>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgVectorLowering (linalg-vector-lowering) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<16xi32>
          %c5 = arith.constant 5 : index
          %c6 = arith.constant 6 : index
          %c7 = arith.constant 7 : index
          %c8 = arith.constant 8 : index
          %c9 = arith.constant 9 : index
          %c10 = arith.constant 10 : index
          %c11 = arith.constant 11 : index
          %c12 = arith.constant 12 : index
          %c13 = arith.constant 13 : index
          %c14 = arith.constant 14 : index
          %c15 = arith.constant 15 : index
          %cst_0 = arith.constant dense<0> : vector<4xi32>
          %c2 = arith.constant 2 : index
          %c3 = arith.constant 3 : index
          %cst_1 = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          scf.for %arg0 = %c0 to %c32 step %c1 {
            scf.for %arg1 = %c0 to %c32 step %c4 {
              %6 = memref.subview %5[%arg0, %arg1, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
              %7 = memref.expand_shape %6 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %cst_1) -> (vector<1x4x4xi32>) {
                %27 = vector.transfer_read %7[%c0, %c0, %arg2, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<1x4x1x4xi32>
                %28 = vector.transpose %27, [0, 1, 3, 2] : vector<1x4x1x4xi32> to vector<1x4x4x1xi32>
                %29 = vector.extract %28[0, 0, 0] : vector<1x4x4x1xi32>
                %30 = vector.extract %arg3[0, 0, 0] : vector<1x4x4xi32>
                %31 = vector.reduction <add>, %29, %30 : vector<1xi32> into i32
                %32 = vector.insertelement %31, %cst[%c0 : index] : vector<16xi32>
                %33 = vector.extract %28[0, 0, 1] : vector<1x4x4x1xi32>
                %34 = vector.extract %arg3[0, 0, 1] : vector<1x4x4xi32>
                %35 = vector.reduction <add>, %33, %34 : vector<1xi32> into i32
                %36 = vector.insertelement %35, %32[%c1 : index] : vector<16xi32>
                %37 = vector.extract %28[0, 0, 2] : vector<1x4x4x1xi32>
                %38 = vector.extract %arg3[0, 0, 2] : vector<1x4x4xi32>
                %39 = vector.reduction <add>, %37, %38 : vector<1xi32> into i32
                %40 = vector.insertelement %39, %36[%c2 : index] : vector<16xi32>
                %41 = vector.extract %28[0, 0, 3] : vector<1x4x4x1xi32>
                %42 = vector.extract %arg3[0, 0, 3] : vector<1x4x4xi32>
                %43 = vector.reduction <add>, %41, %42 : vector<1xi32> into i32
                %44 = vector.insertelement %43, %40[%c3 : index] : vector<16xi32>
                %45 = vector.extract %28[0, 1, 0] : vector<1x4x4x1xi32>
                %46 = vector.extract %arg3[0, 1, 0] : vector<1x4x4xi32>
                %47 = vector.reduction <add>, %45, %46 : vector<1xi32> into i32
                %48 = vector.insertelement %47, %44[%c4 : index] : vector<16xi32>
                %49 = vector.extract %28[0, 1, 1] : vector<1x4x4x1xi32>
                %50 = vector.extract %arg3[0, 1, 1] : vector<1x4x4xi32>
                %51 = vector.reduction <add>, %49, %50 : vector<1xi32> into i32
                %52 = vector.insertelement %51, %48[%c5 : index] : vector<16xi32>
                %53 = vector.extract %28[0, 1, 2] : vector<1x4x4x1xi32>
                %54 = vector.extract %arg3[0, 1, 2] : vector<1x4x4xi32>
                %55 = vector.reduction <add>, %53, %54 : vector<1xi32> into i32
                %56 = vector.insertelement %55, %52[%c6 : index] : vector<16xi32>
                %57 = vector.extract %28[0, 1, 3] : vector<1x4x4x1xi32>
                %58 = vector.extract %arg3[0, 1, 3] : vector<1x4x4xi32>
                %59 = vector.reduction <add>, %57, %58 : vector<1xi32> into i32
                %60 = vector.insertelement %59, %56[%c7 : index] : vector<16xi32>
                %61 = vector.extract %28[0, 2, 0] : vector<1x4x4x1xi32>
                %62 = vector.extract %arg3[0, 2, 0] : vector<1x4x4xi32>
                %63 = vector.reduction <add>, %61, %62 : vector<1xi32> into i32
                %64 = vector.insertelement %63, %60[%c8 : index] : vector<16xi32>
                %65 = vector.extract %28[0, 2, 1] : vector<1x4x4x1xi32>
                %66 = vector.extract %arg3[0, 2, 1] : vector<1x4x4xi32>
                %67 = vector.reduction <add>, %65, %66 : vector<1xi32> into i32
                %68 = vector.insertelement %67, %64[%c9 : index] : vector<16xi32>
                %69 = vector.extract %28[0, 2, 2] : vector<1x4x4x1xi32>
                %70 = vector.extract %arg3[0, 2, 2] : vector<1x4x4xi32>
                %71 = vector.reduction <add>, %69, %70 : vector<1xi32> into i32
                %72 = vector.insertelement %71, %68[%c10 : index] : vector<16xi32>
                %73 = vector.extract %28[0, 2, 3] : vector<1x4x4x1xi32>
                %74 = vector.extract %arg3[0, 2, 3] : vector<1x4x4xi32>
                %75 = vector.reduction <add>, %73, %74 : vector<1xi32> into i32
                %76 = vector.insertelement %75, %72[%c11 : index] : vector<16xi32>
                %77 = vector.extract %28[0, 3, 0] : vector<1x4x4x1xi32>
                %78 = vector.extract %arg3[0, 3, 0] : vector<1x4x4xi32>
                %79 = vector.reduction <add>, %77, %78 : vector<1xi32> into i32
                %80 = vector.insertelement %79, %76[%c12 : index] : vector<16xi32>
                %81 = vector.extract %28[0, 3, 1] : vector<1x4x4x1xi32>
                %82 = vector.extract %arg3[0, 3, 1] : vector<1x4x4xi32>
                %83 = vector.reduction <add>, %81, %82 : vector<1xi32> into i32
                %84 = vector.insertelement %83, %80[%c13 : index] : vector<16xi32>
                %85 = vector.extract %28[0, 3, 2] : vector<1x4x4x1xi32>
                %86 = vector.extract %arg3[0, 3, 2] : vector<1x4x4xi32>
                %87 = vector.reduction <add>, %85, %86 : vector<1xi32> into i32
                %88 = vector.insertelement %87, %84[%c14 : index] : vector<16xi32>
                %89 = vector.extract %28[0, 3, 3] : vector<1x4x4x1xi32>
                %90 = vector.extract %arg3[0, 3, 3] : vector<1x4x4xi32>
                %91 = vector.reduction <add>, %89, %90 : vector<1xi32> into i32
                %92 = vector.insertelement %91, %88[%c15 : index] : vector<16xi32>
                %93 = vector.shape_cast %92 : vector<16xi32> to vector<1x4x4xi32>
                scf.yield %93 : vector<1x4x4xi32>
              }
              %9 = vector.transfer_read %4[%arg0, %arg1], %c0_i32 {in_bounds = [true, true]} : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<1x4xi32>
              %10 = vector.extract %8[0, 0] : vector<1x4x4xi32>
              %11 = vector.extract %9[0, 0] : vector<1x4xi32>
              %12 = vector.reduction <add>, %10, %11 : vector<4xi32> into i32
              %13 = vector.insertelement %12, %cst_0[%c0 : index] : vector<4xi32>
              %14 = vector.extract %8[0, 1] : vector<1x4x4xi32>
              %15 = vector.extract %9[0, 1] : vector<1x4xi32>
              %16 = vector.reduction <add>, %14, %15 : vector<4xi32> into i32
              %17 = vector.insertelement %16, %13[%c1 : index] : vector<4xi32>
              %18 = vector.extract %8[0, 2] : vector<1x4x4xi32>
              %19 = vector.extract %9[0, 2] : vector<1x4xi32>
              %20 = vector.reduction <add>, %18, %19 : vector<4xi32> into i32
              %21 = vector.insertelement %20, %17[%c2 : index] : vector<4xi32>
              %22 = vector.extract %8[0, 3] : vector<1x4x4xi32>
              %23 = vector.extract %9[0, 3] : vector<1x4xi32>
              %24 = vector.reduction <add>, %22, %23 : vector<4xi32> into i32
              %25 = vector.insertelement %24, %21[%c3 : index] : vector<4xi32>
              %26 = vector.shape_cast %25 : vector<4xi32> to vector<1x4xi32>
              vector.transfer_write %26, %4[%arg0, %arg1] {in_bounds = [true, true]} : vector<1x4xi32>, memref<32x32xi32, strided<[256, 1], offset: ?>>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<16xi32>
          %c5 = arith.constant 5 : index
          %c6 = arith.constant 6 : index
          %c7 = arith.constant 7 : index
          %c8 = arith.constant 8 : index
          %c9 = arith.constant 9 : index
          %c10 = arith.constant 10 : index
          %c11 = arith.constant 11 : index
          %c12 = arith.constant 12 : index
          %c13 = arith.constant 13 : index
          %c14 = arith.constant 14 : index
          %c15 = arith.constant 15 : index
          %cst_0 = arith.constant dense<0> : vector<4xi32>
          %c2 = arith.constant 2 : index
          %c3 = arith.constant 3 : index
          %cst_1 = arith.constant dense<0> : vector<1x4x4xi32>
          %c0_i32 = arith.constant 0 : i32
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          scf.for %arg0 = %c0 to %c32 step %c1 {
            scf.for %arg1 = %c0 to %c32 step %c4 {
              %6 = memref.subview %5[%arg0, %arg1, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
              %7 = memref.expand_shape %6 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %cst_1) -> (vector<1x4x4xi32>) {
                %27 = vector.transfer_read %7[%c0, %c0, %arg2, %c0], %c0_i32 {in_bounds = [true, true, true, true]} : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<1x4x1x4xi32>
                %28 = vector.extract %arg3[0, 0, 0] : vector<1x4x4xi32>
                %29 = vector.extract %27[0, 0, 0, 0] : vector<1x4x1x4xi32>
                %30 = arith.addi %29, %28 : i32
                %31 = vector.insertelement %30, %cst[%c0 : index] : vector<16xi32>
                %32 = vector.extract %arg3[0, 0, 1] : vector<1x4x4xi32>
                %33 = vector.extract %27[0, 0, 0, 1] : vector<1x4x1x4xi32>
                %34 = arith.addi %33, %32 : i32
                %35 = vector.insertelement %34, %31[%c1 : index] : vector<16xi32>
                %36 = vector.extract %arg3[0, 0, 2] : vector<1x4x4xi32>
                %37 = vector.extract %27[0, 0, 0, 2] : vector<1x4x1x4xi32>
                %38 = arith.addi %37, %36 : i32
                %39 = vector.insertelement %38, %35[%c2 : index] : vector<16xi32>
                %40 = vector.extract %arg3[0, 0, 3] : vector<1x4x4xi32>
                %41 = vector.extract %27[0, 0, 0, 3] : vector<1x4x1x4xi32>
                %42 = arith.addi %41, %40 : i32
                %43 = vector.insertelement %42, %39[%c3 : index] : vector<16xi32>
                %44 = vector.extract %arg3[0, 1, 0] : vector<1x4x4xi32>
                %45 = vector.extract %27[0, 1, 0, 0] : vector<1x4x1x4xi32>
                %46 = arith.addi %45, %44 : i32
                %47 = vector.insertelement %46, %43[%c4 : index] : vector<16xi32>
                %48 = vector.extract %arg3[0, 1, 1] : vector<1x4x4xi32>
                %49 = vector.extract %27[0, 1, 0, 1] : vector<1x4x1x4xi32>
                %50 = arith.addi %49, %48 : i32
                %51 = vector.insertelement %50, %47[%c5 : index] : vector<16xi32>
                %52 = vector.extract %arg3[0, 1, 2] : vector<1x4x4xi32>
                %53 = vector.extract %27[0, 1, 0, 2] : vector<1x4x1x4xi32>
                %54 = arith.addi %53, %52 : i32
                %55 = vector.insertelement %54, %51[%c6 : index] : vector<16xi32>
                %56 = vector.extract %arg3[0, 1, 3] : vector<1x4x4xi32>
                %57 = vector.extract %27[0, 1, 0, 3] : vector<1x4x1x4xi32>
                %58 = arith.addi %57, %56 : i32
                %59 = vector.insertelement %58, %55[%c7 : index] : vector<16xi32>
                %60 = vector.extract %arg3[0, 2, 0] : vector<1x4x4xi32>
                %61 = vector.extract %27[0, 2, 0, 0] : vector<1x4x1x4xi32>
                %62 = arith.addi %61, %60 : i32
                %63 = vector.insertelement %62, %59[%c8 : index] : vector<16xi32>
                %64 = vector.extract %arg3[0, 2, 1] : vector<1x4x4xi32>
                %65 = vector.extract %27[0, 2, 0, 1] : vector<1x4x1x4xi32>
                %66 = arith.addi %65, %64 : i32
                %67 = vector.insertelement %66, %63[%c9 : index] : vector<16xi32>
                %68 = vector.extract %arg3[0, 2, 2] : vector<1x4x4xi32>
                %69 = vector.extract %27[0, 2, 0, 2] : vector<1x4x1x4xi32>
                %70 = arith.addi %69, %68 : i32
                %71 = vector.insertelement %70, %67[%c10 : index] : vector<16xi32>
                %72 = vector.extract %arg3[0, 2, 3] : vector<1x4x4xi32>
                %73 = vector.extract %27[0, 2, 0, 3] : vector<1x4x1x4xi32>
                %74 = arith.addi %73, %72 : i32
                %75 = vector.insertelement %74, %71[%c11 : index] : vector<16xi32>
                %76 = vector.extract %arg3[0, 3, 0] : vector<1x4x4xi32>
                %77 = vector.extract %27[0, 3, 0, 0] : vector<1x4x1x4xi32>
                %78 = arith.addi %77, %76 : i32
                %79 = vector.insertelement %78, %75[%c12 : index] : vector<16xi32>
                %80 = vector.extract %arg3[0, 3, 1] : vector<1x4x4xi32>
                %81 = vector.extract %27[0, 3, 0, 1] : vector<1x4x1x4xi32>
                %82 = arith.addi %81, %80 : i32
                %83 = vector.insertelement %82, %79[%c13 : index] : vector<16xi32>
                %84 = vector.extract %arg3[0, 3, 2] : vector<1x4x4xi32>
                %85 = vector.extract %27[0, 3, 0, 2] : vector<1x4x1x4xi32>
                %86 = arith.addi %85, %84 : i32
                %87 = vector.insertelement %86, %83[%c14 : index] : vector<16xi32>
                %88 = vector.extract %arg3[0, 3, 3] : vector<1x4x4xi32>
                %89 = vector.extract %27[0, 3, 0, 3] : vector<1x4x1x4xi32>
                %90 = arith.addi %89, %88 : i32
                %91 = vector.insertelement %90, %87[%c15 : index] : vector<16xi32>
                %92 = vector.shape_cast %91 : vector<16xi32> to vector<1x4x4xi32>
                scf.yield %92 : vector<1x4x4xi32>
              }
              %9 = vector.transfer_read %4[%arg0, %arg1], %c0_i32 {in_bounds = [true, true]} : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<1x4xi32>
              %10 = vector.extract %8[0, 0] : vector<1x4x4xi32>
              %11 = vector.extract %9[0, 0] : vector<1x4xi32>
              %12 = vector.reduction <add>, %10, %11 : vector<4xi32> into i32
              %13 = vector.insertelement %12, %cst_0[%c0 : index] : vector<4xi32>
              %14 = vector.extract %8[0, 1] : vector<1x4x4xi32>
              %15 = vector.extract %9[0, 1] : vector<1x4xi32>
              %16 = vector.reduction <add>, %14, %15 : vector<4xi32> into i32
              %17 = vector.insertelement %16, %13[%c1 : index] : vector<4xi32>
              %18 = vector.extract %8[0, 2] : vector<1x4x4xi32>
              %19 = vector.extract %9[0, 2] : vector<1x4xi32>
              %20 = vector.reduction <add>, %18, %19 : vector<4xi32> into i32
              %21 = vector.insertelement %20, %17[%c2 : index] : vector<4xi32>
              %22 = vector.extract %8[0, 3] : vector<1x4x4xi32>
              %23 = vector.extract %9[0, 3] : vector<1x4xi32>
              %24 = vector.reduction <add>, %22, %23 : vector<4xi32> into i32
              %25 = vector.insertelement %24, %21[%c3 : index] : vector<4xi32>
              %26 = vector.shape_cast %25 : vector<4xi32> to vector<1x4xi32>
              vector.transfer_write %26, %4[%arg0, %arg1] {in_bounds = [true, true]} : vector<1x4xi32>, memref<32x32xi32, strided<[256, 1], offset: ?>>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgStrategyLowerVectorsPass (iree-linalg-strategy-lower-vectors-pass) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<16xi32>
          %c5 = arith.constant 5 : index
          %c6 = arith.constant 6 : index
          %c7 = arith.constant 7 : index
          %c8 = arith.constant 8 : index
          %c9 = arith.constant 9 : index
          %c10 = arith.constant 10 : index
          %c11 = arith.constant 11 : index
          %c12 = arith.constant 12 : index
          %c13 = arith.constant 13 : index
          %c14 = arith.constant 14 : index
          %c15 = arith.constant 15 : index
          %cst_0 = arith.constant dense<0> : vector<4xi32>
          %c2 = arith.constant 2 : index
          %c3 = arith.constant 3 : index
          %cst_1 = arith.constant dense<0> : vector<1x4x4xi32>
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          scf.for %arg0 = %c0 to %c32 step %c1 {
            scf.for %arg1 = %c0 to %c32 step %c4 {
              %6 = memref.subview %5[%arg0, %arg1, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
              %7 = memref.expand_shape %6 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %cst_1) -> (vector<1x4x4xi32>) {
                %26 = vector.load %7[%c0, %c0, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %27 = vector.load %7[%c0, %c1, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %28 = vector.load %7[%c0, %c2, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %29 = vector.load %7[%c0, %c3, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %30 = vector.extract %arg3[0, 0, 0] : vector<1x4x4xi32>
                %31 = vector.extract %26[0] : vector<4xi32>
                %32 = arith.addi %31, %30 : i32
                %33 = vector.insertelement %32, %cst[%c0 : index] : vector<16xi32>
                %34 = vector.extract %arg3[0, 0, 1] : vector<1x4x4xi32>
                %35 = vector.extract %26[1] : vector<4xi32>
                %36 = arith.addi %35, %34 : i32
                %37 = vector.insertelement %36, %33[%c1 : index] : vector<16xi32>
                %38 = vector.extract %arg3[0, 0, 2] : vector<1x4x4xi32>
                %39 = vector.extract %26[2] : vector<4xi32>
                %40 = arith.addi %39, %38 : i32
                %41 = vector.insertelement %40, %37[%c2 : index] : vector<16xi32>
                %42 = vector.extract %arg3[0, 0, 3] : vector<1x4x4xi32>
                %43 = vector.extract %26[3] : vector<4xi32>
                %44 = arith.addi %43, %42 : i32
                %45 = vector.insertelement %44, %41[%c3 : index] : vector<16xi32>
                %46 = vector.extract %arg3[0, 1, 0] : vector<1x4x4xi32>
                %47 = vector.extract %27[0] : vector<4xi32>
                %48 = arith.addi %47, %46 : i32
                %49 = vector.insertelement %48, %45[%c4 : index] : vector<16xi32>
                %50 = vector.extract %arg3[0, 1, 1] : vector<1x4x4xi32>
                %51 = vector.extract %27[1] : vector<4xi32>
                %52 = arith.addi %51, %50 : i32
                %53 = vector.insertelement %52, %49[%c5 : index] : vector<16xi32>
                %54 = vector.extract %arg3[0, 1, 2] : vector<1x4x4xi32>
                %55 = vector.extract %27[2] : vector<4xi32>
                %56 = arith.addi %55, %54 : i32
                %57 = vector.insertelement %56, %53[%c6 : index] : vector<16xi32>
                %58 = vector.extract %arg3[0, 1, 3] : vector<1x4x4xi32>
                %59 = vector.extract %27[3] : vector<4xi32>
                %60 = arith.addi %59, %58 : i32
                %61 = vector.insertelement %60, %57[%c7 : index] : vector<16xi32>
                %62 = vector.extract %arg3[0, 2, 0] : vector<1x4x4xi32>
                %63 = vector.extract %28[0] : vector<4xi32>
                %64 = arith.addi %63, %62 : i32
                %65 = vector.insertelement %64, %61[%c8 : index] : vector<16xi32>
                %66 = vector.extract %arg3[0, 2, 1] : vector<1x4x4xi32>
                %67 = vector.extract %28[1] : vector<4xi32>
                %68 = arith.addi %67, %66 : i32
                %69 = vector.insertelement %68, %65[%c9 : index] : vector<16xi32>
                %70 = vector.extract %arg3[0, 2, 2] : vector<1x4x4xi32>
                %71 = vector.extract %28[2] : vector<4xi32>
                %72 = arith.addi %71, %70 : i32
                %73 = vector.insertelement %72, %69[%c10 : index] : vector<16xi32>
                %74 = vector.extract %arg3[0, 2, 3] : vector<1x4x4xi32>
                %75 = vector.extract %28[3] : vector<4xi32>
                %76 = arith.addi %75, %74 : i32
                %77 = vector.insertelement %76, %73[%c11 : index] : vector<16xi32>
                %78 = vector.extract %arg3[0, 3, 0] : vector<1x4x4xi32>
                %79 = vector.extract %29[0] : vector<4xi32>
                %80 = arith.addi %79, %78 : i32
                %81 = vector.insertelement %80, %77[%c12 : index] : vector<16xi32>
                %82 = vector.extract %arg3[0, 3, 1] : vector<1x4x4xi32>
                %83 = vector.extract %29[1] : vector<4xi32>
                %84 = arith.addi %83, %82 : i32
                %85 = vector.insertelement %84, %81[%c13 : index] : vector<16xi32>
                %86 = vector.extract %arg3[0, 3, 2] : vector<1x4x4xi32>
                %87 = vector.extract %29[2] : vector<4xi32>
                %88 = arith.addi %87, %86 : i32
                %89 = vector.insertelement %88, %85[%c14 : index] : vector<16xi32>
                %90 = vector.extract %arg3[0, 3, 3] : vector<1x4x4xi32>
                %91 = vector.extract %29[3] : vector<4xi32>
                %92 = arith.addi %91, %90 : i32
                %93 = vector.insertelement %92, %89[%c15 : index] : vector<16xi32>
                %94 = vector.shape_cast %93 : vector<16xi32> to vector<1x4x4xi32>
                scf.yield %94 : vector<1x4x4xi32>
              }
              %9 = vector.load %4[%arg0, %arg1] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
              %10 = vector.extract %8[0, 0] : vector<1x4x4xi32>
              %11 = vector.extract %9[0] : vector<4xi32>
              %12 = vector.reduction <add>, %10, %11 : vector<4xi32> into i32
              %13 = vector.insertelement %12, %cst_0[%c0 : index] : vector<4xi32>
              %14 = vector.extract %8[0, 1] : vector<1x4x4xi32>
              %15 = vector.extract %9[1] : vector<4xi32>
              %16 = vector.reduction <add>, %14, %15 : vector<4xi32> into i32
              %17 = vector.insertelement %16, %13[%c1 : index] : vector<4xi32>
              %18 = vector.extract %8[0, 2] : vector<1x4x4xi32>
              %19 = vector.extract %9[2] : vector<4xi32>
              %20 = vector.reduction <add>, %18, %19 : vector<4xi32> into i32
              %21 = vector.insertelement %20, %17[%c2 : index] : vector<4xi32>
              %22 = vector.extract %8[0, 3] : vector<1x4x4xi32>
              %23 = vector.extract %9[3] : vector<4xi32>
              %24 = vector.reduction <add>, %22, %23 : vector<4xi32> into i32
              %25 = vector.insertelement %24, %21[%c3 : index] : vector<4xi32>
              vector.store %25, %4[%arg0, %arg1] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgVectorLowering (linalg-vector-lowering) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<16xi32>
          %c5 = arith.constant 5 : index
          %c6 = arith.constant 6 : index
          %c7 = arith.constant 7 : index
          %c8 = arith.constant 8 : index
          %c9 = arith.constant 9 : index
          %c10 = arith.constant 10 : index
          %c11 = arith.constant 11 : index
          %c12 = arith.constant 12 : index
          %c13 = arith.constant 13 : index
          %c14 = arith.constant 14 : index
          %c15 = arith.constant 15 : index
          %cst_0 = arith.constant dense<0> : vector<4xi32>
          %c2 = arith.constant 2 : index
          %c3 = arith.constant 3 : index
          %cst_1 = arith.constant dense<0> : vector<1x4x4xi32>
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          scf.for %arg0 = %c0 to %c32 step %c1 {
            scf.for %arg1 = %c0 to %c32 step %c4 {
              %6 = memref.subview %5[%arg0, %arg1, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
              %7 = memref.expand_shape %6 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %cst_1) -> (vector<1x4x4xi32>) {
                %26 = vector.load %7[%c0, %c0, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %27 = vector.load %7[%c0, %c1, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %28 = vector.load %7[%c0, %c2, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %29 = vector.load %7[%c0, %c3, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %30 = vector.extract %arg3[0, 0, 0] : vector<1x4x4xi32>
                %31 = vector.extract %26[0] : vector<4xi32>
                %32 = arith.addi %31, %30 : i32
                %33 = vector.insertelement %32, %cst[%c0 : index] : vector<16xi32>
                %34 = vector.extract %arg3[0, 0, 1] : vector<1x4x4xi32>
                %35 = vector.extract %26[1] : vector<4xi32>
                %36 = arith.addi %35, %34 : i32
                %37 = vector.insertelement %36, %33[%c1 : index] : vector<16xi32>
                %38 = vector.extract %arg3[0, 0, 2] : vector<1x4x4xi32>
                %39 = vector.extract %26[2] : vector<4xi32>
                %40 = arith.addi %39, %38 : i32
                %41 = vector.insertelement %40, %37[%c2 : index] : vector<16xi32>
                %42 = vector.extract %arg3[0, 0, 3] : vector<1x4x4xi32>
                %43 = vector.extract %26[3] : vector<4xi32>
                %44 = arith.addi %43, %42 : i32
                %45 = vector.insertelement %44, %41[%c3 : index] : vector<16xi32>
                %46 = vector.extract %arg3[0, 1, 0] : vector<1x4x4xi32>
                %47 = vector.extract %27[0] : vector<4xi32>
                %48 = arith.addi %47, %46 : i32
                %49 = vector.insertelement %48, %45[%c4 : index] : vector<16xi32>
                %50 = vector.extract %arg3[0, 1, 1] : vector<1x4x4xi32>
                %51 = vector.extract %27[1] : vector<4xi32>
                %52 = arith.addi %51, %50 : i32
                %53 = vector.insertelement %52, %49[%c5 : index] : vector<16xi32>
                %54 = vector.extract %arg3[0, 1, 2] : vector<1x4x4xi32>
                %55 = vector.extract %27[2] : vector<4xi32>
                %56 = arith.addi %55, %54 : i32
                %57 = vector.insertelement %56, %53[%c6 : index] : vector<16xi32>
                %58 = vector.extract %arg3[0, 1, 3] : vector<1x4x4xi32>
                %59 = vector.extract %27[3] : vector<4xi32>
                %60 = arith.addi %59, %58 : i32
                %61 = vector.insertelement %60, %57[%c7 : index] : vector<16xi32>
                %62 = vector.extract %arg3[0, 2, 0] : vector<1x4x4xi32>
                %63 = vector.extract %28[0] : vector<4xi32>
                %64 = arith.addi %63, %62 : i32
                %65 = vector.insertelement %64, %61[%c8 : index] : vector<16xi32>
                %66 = vector.extract %arg3[0, 2, 1] : vector<1x4x4xi32>
                %67 = vector.extract %28[1] : vector<4xi32>
                %68 = arith.addi %67, %66 : i32
                %69 = vector.insertelement %68, %65[%c9 : index] : vector<16xi32>
                %70 = vector.extract %arg3[0, 2, 2] : vector<1x4x4xi32>
                %71 = vector.extract %28[2] : vector<4xi32>
                %72 = arith.addi %71, %70 : i32
                %73 = vector.insertelement %72, %69[%c10 : index] : vector<16xi32>
                %74 = vector.extract %arg3[0, 2, 3] : vector<1x4x4xi32>
                %75 = vector.extract %28[3] : vector<4xi32>
                %76 = arith.addi %75, %74 : i32
                %77 = vector.insertelement %76, %73[%c11 : index] : vector<16xi32>
                %78 = vector.extract %arg3[0, 3, 0] : vector<1x4x4xi32>
                %79 = vector.extract %29[0] : vector<4xi32>
                %80 = arith.addi %79, %78 : i32
                %81 = vector.insertelement %80, %77[%c12 : index] : vector<16xi32>
                %82 = vector.extract %arg3[0, 3, 1] : vector<1x4x4xi32>
                %83 = vector.extract %29[1] : vector<4xi32>
                %84 = arith.addi %83, %82 : i32
                %85 = vector.insertelement %84, %81[%c13 : index] : vector<16xi32>
                %86 = vector.extract %arg3[0, 3, 2] : vector<1x4x4xi32>
                %87 = vector.extract %29[2] : vector<4xi32>
                %88 = arith.addi %87, %86 : i32
                %89 = vector.insertelement %88, %85[%c14 : index] : vector<16xi32>
                %90 = vector.extract %arg3[0, 3, 3] : vector<1x4x4xi32>
                %91 = vector.extract %29[3] : vector<4xi32>
                %92 = arith.addi %91, %90 : i32
                %93 = vector.insertelement %92, %89[%c15 : index] : vector<16xi32>
                %94 = vector.shape_cast %93 : vector<16xi32> to vector<1x4x4xi32>
                scf.yield %94 : vector<1x4x4xi32>
              }
              %9 = vector.load %4[%arg0, %arg1] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
              %10 = vector.extract %8[0, 0] : vector<1x4x4xi32>
              %11 = vector.extract %9[0] : vector<4xi32>
              %12 = vector.reduction <add>, %10, %11 : vector<4xi32> into i32
              %13 = vector.insertelement %12, %cst_0[%c0 : index] : vector<4xi32>
              %14 = vector.extract %8[0, 1] : vector<1x4x4xi32>
              %15 = vector.extract %9[1] : vector<4xi32>
              %16 = vector.reduction <add>, %14, %15 : vector<4xi32> into i32
              %17 = vector.insertelement %16, %13[%c1 : index] : vector<4xi32>
              %18 = vector.extract %8[0, 2] : vector<1x4x4xi32>
              %19 = vector.extract %9[2] : vector<4xi32>
              %20 = vector.reduction <add>, %18, %19 : vector<4xi32> into i32
              %21 = vector.insertelement %20, %17[%c2 : index] : vector<4xi32>
              %22 = vector.extract %8[0, 3] : vector<1x4x4xi32>
              %23 = vector.extract %9[3] : vector<4xi32>
              %24 = vector.reduction <add>, %22, %23 : vector<4xi32> into i32
              %25 = vector.insertelement %24, %21[%c3 : index] : vector<4xi32>
              vector.store %25, %4[%arg0, %arg1] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgStrategyLowerVectorsPass (iree-linalg-strategy-lower-vectors-pass) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<16xi32>
          %c5 = arith.constant 5 : index
          %c6 = arith.constant 6 : index
          %c7 = arith.constant 7 : index
          %c8 = arith.constant 8 : index
          %c9 = arith.constant 9 : index
          %c10 = arith.constant 10 : index
          %c11 = arith.constant 11 : index
          %c12 = arith.constant 12 : index
          %c13 = arith.constant 13 : index
          %c14 = arith.constant 14 : index
          %c15 = arith.constant 15 : index
          %cst_0 = arith.constant dense<0> : vector<4xi32>
          %c2 = arith.constant 2 : index
          %c3 = arith.constant 3 : index
          %cst_1 = arith.constant dense<0> : vector<1x4x4xi32>
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          scf.for %arg0 = %c0 to %c32 step %c1 {
            scf.for %arg1 = %c0 to %c32 step %c4 {
              %6 = memref.subview %5[%arg0, %arg1, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
              %7 = memref.expand_shape %6 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %cst_1) -> (vector<1x4x4xi32>) {
                %26 = vector.load %7[%c0, %c0, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %27 = vector.load %7[%c0, %c1, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %28 = vector.load %7[%c0, %c2, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %29 = vector.load %7[%c0, %c3, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %30 = vector.extract %arg3[0, 0, 0] : vector<1x4x4xi32>
                %31 = vector.extract %26[0] : vector<4xi32>
                %32 = arith.addi %31, %30 : i32
                %33 = vector.insertelement %32, %cst[%c0 : index] : vector<16xi32>
                %34 = vector.extract %arg3[0, 0, 1] : vector<1x4x4xi32>
                %35 = vector.extract %26[1] : vector<4xi32>
                %36 = arith.addi %35, %34 : i32
                %37 = vector.insertelement %36, %33[%c1 : index] : vector<16xi32>
                %38 = vector.extract %arg3[0, 0, 2] : vector<1x4x4xi32>
                %39 = vector.extract %26[2] : vector<4xi32>
                %40 = arith.addi %39, %38 : i32
                %41 = vector.insertelement %40, %37[%c2 : index] : vector<16xi32>
                %42 = vector.extract %arg3[0, 0, 3] : vector<1x4x4xi32>
                %43 = vector.extract %26[3] : vector<4xi32>
                %44 = arith.addi %43, %42 : i32
                %45 = vector.insertelement %44, %41[%c3 : index] : vector<16xi32>
                %46 = vector.extract %arg3[0, 1, 0] : vector<1x4x4xi32>
                %47 = vector.extract %27[0] : vector<4xi32>
                %48 = arith.addi %47, %46 : i32
                %49 = vector.insertelement %48, %45[%c4 : index] : vector<16xi32>
                %50 = vector.extract %arg3[0, 1, 1] : vector<1x4x4xi32>
                %51 = vector.extract %27[1] : vector<4xi32>
                %52 = arith.addi %51, %50 : i32
                %53 = vector.insertelement %52, %49[%c5 : index] : vector<16xi32>
                %54 = vector.extract %arg3[0, 1, 2] : vector<1x4x4xi32>
                %55 = vector.extract %27[2] : vector<4xi32>
                %56 = arith.addi %55, %54 : i32
                %57 = vector.insertelement %56, %53[%c6 : index] : vector<16xi32>
                %58 = vector.extract %arg3[0, 1, 3] : vector<1x4x4xi32>
                %59 = vector.extract %27[3] : vector<4xi32>
                %60 = arith.addi %59, %58 : i32
                %61 = vector.insertelement %60, %57[%c7 : index] : vector<16xi32>
                %62 = vector.extract %arg3[0, 2, 0] : vector<1x4x4xi32>
                %63 = vector.extract %28[0] : vector<4xi32>
                %64 = arith.addi %63, %62 : i32
                %65 = vector.insertelement %64, %61[%c8 : index] : vector<16xi32>
                %66 = vector.extract %arg3[0, 2, 1] : vector<1x4x4xi32>
                %67 = vector.extract %28[1] : vector<4xi32>
                %68 = arith.addi %67, %66 : i32
                %69 = vector.insertelement %68, %65[%c9 : index] : vector<16xi32>
                %70 = vector.extract %arg3[0, 2, 2] : vector<1x4x4xi32>
                %71 = vector.extract %28[2] : vector<4xi32>
                %72 = arith.addi %71, %70 : i32
                %73 = vector.insertelement %72, %69[%c10 : index] : vector<16xi32>
                %74 = vector.extract %arg3[0, 2, 3] : vector<1x4x4xi32>
                %75 = vector.extract %28[3] : vector<4xi32>
                %76 = arith.addi %75, %74 : i32
                %77 = vector.insertelement %76, %73[%c11 : index] : vector<16xi32>
                %78 = vector.extract %arg3[0, 3, 0] : vector<1x4x4xi32>
                %79 = vector.extract %29[0] : vector<4xi32>
                %80 = arith.addi %79, %78 : i32
                %81 = vector.insertelement %80, %77[%c12 : index] : vector<16xi32>
                %82 = vector.extract %arg3[0, 3, 1] : vector<1x4x4xi32>
                %83 = vector.extract %29[1] : vector<4xi32>
                %84 = arith.addi %83, %82 : i32
                %85 = vector.insertelement %84, %81[%c13 : index] : vector<16xi32>
                %86 = vector.extract %arg3[0, 3, 2] : vector<1x4x4xi32>
                %87 = vector.extract %29[2] : vector<4xi32>
                %88 = arith.addi %87, %86 : i32
                %89 = vector.insertelement %88, %85[%c14 : index] : vector<16xi32>
                %90 = vector.extract %arg3[0, 3, 3] : vector<1x4x4xi32>
                %91 = vector.extract %29[3] : vector<4xi32>
                %92 = arith.addi %91, %90 : i32
                %93 = vector.insertelement %92, %89[%c15 : index] : vector<16xi32>
                %94 = vector.extract %93[0] : vector<16xi32>
                %95 = vector.insert %94, %cst_1 [0, 0, 0] : i32 into vector<1x4x4xi32>
                %96 = vector.extract %93[1] : vector<16xi32>
                %97 = vector.insert %96, %95 [0, 0, 1] : i32 into vector<1x4x4xi32>
                %98 = vector.extract %93[2] : vector<16xi32>
                %99 = vector.insert %98, %97 [0, 0, 2] : i32 into vector<1x4x4xi32>
                %100 = vector.extract %93[3] : vector<16xi32>
                %101 = vector.insert %100, %99 [0, 0, 3] : i32 into vector<1x4x4xi32>
                %102 = vector.extract %93[4] : vector<16xi32>
                %103 = vector.insert %102, %101 [0, 1, 0] : i32 into vector<1x4x4xi32>
                %104 = vector.extract %93[5] : vector<16xi32>
                %105 = vector.insert %104, %103 [0, 1, 1] : i32 into vector<1x4x4xi32>
                %106 = vector.extract %93[6] : vector<16xi32>
                %107 = vector.insert %106, %105 [0, 1, 2] : i32 into vector<1x4x4xi32>
                %108 = vector.extract %93[7] : vector<16xi32>
                %109 = vector.insert %108, %107 [0, 1, 3] : i32 into vector<1x4x4xi32>
                %110 = vector.extract %93[8] : vector<16xi32>
                %111 = vector.insert %110, %109 [0, 2, 0] : i32 into vector<1x4x4xi32>
                %112 = vector.extract %93[9] : vector<16xi32>
                %113 = vector.insert %112, %111 [0, 2, 1] : i32 into vector<1x4x4xi32>
                %114 = vector.extract %93[10] : vector<16xi32>
                %115 = vector.insert %114, %113 [0, 2, 2] : i32 into vector<1x4x4xi32>
                %116 = vector.extract %93[11] : vector<16xi32>
                %117 = vector.insert %116, %115 [0, 2, 3] : i32 into vector<1x4x4xi32>
                %118 = vector.extract %93[12] : vector<16xi32>
                %119 = vector.insert %118, %117 [0, 3, 0] : i32 into vector<1x4x4xi32>
                %120 = vector.extract %93[13] : vector<16xi32>
                %121 = vector.insert %120, %119 [0, 3, 1] : i32 into vector<1x4x4xi32>
                %122 = vector.extract %93[14] : vector<16xi32>
                %123 = vector.insert %122, %121 [0, 3, 2] : i32 into vector<1x4x4xi32>
                %124 = vector.extract %93[15] : vector<16xi32>
                %125 = vector.insert %124, %123 [0, 3, 3] : i32 into vector<1x4x4xi32>
                scf.yield %125 : vector<1x4x4xi32>
              }
              %9 = vector.load %4[%arg0, %arg1] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
              %10 = vector.extract %8[0, 0] : vector<1x4x4xi32>
              %11 = vector.extract %9[0] : vector<4xi32>
              %12 = vector.reduction <add>, %10, %11 : vector<4xi32> into i32
              %13 = vector.insertelement %12, %cst_0[%c0 : index] : vector<4xi32>
              %14 = vector.extract %8[0, 1] : vector<1x4x4xi32>
              %15 = vector.extract %9[1] : vector<4xi32>
              %16 = vector.reduction <add>, %14, %15 : vector<4xi32> into i32
              %17 = vector.insertelement %16, %13[%c1 : index] : vector<4xi32>
              %18 = vector.extract %8[0, 2] : vector<1x4x4xi32>
              %19 = vector.extract %9[2] : vector<4xi32>
              %20 = vector.reduction <add>, %18, %19 : vector<4xi32> into i32
              %21 = vector.insertelement %20, %17[%c2 : index] : vector<4xi32>
              %22 = vector.extract %8[0, 3] : vector<1x4x4xi32>
              %23 = vector.extract %9[3] : vector<4xi32>
              %24 = vector.reduction <add>, %22, %23 : vector<4xi32> into i32
              %25 = vector.insertelement %24, %21[%c3 : index] : vector<4xi32>
              vector.store %25, %4[%arg0, %arg1] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LinalgVectorLowering (linalg-vector-lowering) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<16xi32>
          %c5 = arith.constant 5 : index
          %c6 = arith.constant 6 : index
          %c7 = arith.constant 7 : index
          %c8 = arith.constant 8 : index
          %c9 = arith.constant 9 : index
          %c10 = arith.constant 10 : index
          %c11 = arith.constant 11 : index
          %c12 = arith.constant 12 : index
          %c13 = arith.constant 13 : index
          %c14 = arith.constant 14 : index
          %c15 = arith.constant 15 : index
          %cst_0 = arith.constant dense<0> : vector<4xi32>
          %c2 = arith.constant 2 : index
          %c3 = arith.constant 3 : index
          %cst_1 = arith.constant dense<0> : vector<1x4x4xi32>
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          scf.for %arg0 = %c0 to %c32 step %c1 {
            scf.for %arg1 = %c0 to %c32 step %c4 {
              %6 = memref.subview %5[%arg0, %arg1, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
              %7 = memref.expand_shape %6 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %cst_1) -> (vector<1x4x4xi32>) {
                %26 = vector.load %7[%c0, %c0, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %27 = vector.load %7[%c0, %c1, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %28 = vector.load %7[%c0, %c2, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %29 = vector.load %7[%c0, %c3, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %30 = vector.extract %arg3[0, 0, 0] : vector<1x4x4xi32>
                %31 = vector.extract %26[0] : vector<4xi32>
                %32 = arith.addi %31, %30 : i32
                %33 = vector.insertelement %32, %cst[%c0 : index] : vector<16xi32>
                %34 = vector.extract %arg3[0, 0, 1] : vector<1x4x4xi32>
                %35 = vector.extract %26[1] : vector<4xi32>
                %36 = arith.addi %35, %34 : i32
                %37 = vector.insertelement %36, %33[%c1 : index] : vector<16xi32>
                %38 = vector.extract %arg3[0, 0, 2] : vector<1x4x4xi32>
                %39 = vector.extract %26[2] : vector<4xi32>
                %40 = arith.addi %39, %38 : i32
                %41 = vector.insertelement %40, %37[%c2 : index] : vector<16xi32>
                %42 = vector.extract %arg3[0, 0, 3] : vector<1x4x4xi32>
                %43 = vector.extract %26[3] : vector<4xi32>
                %44 = arith.addi %43, %42 : i32
                %45 = vector.insertelement %44, %41[%c3 : index] : vector<16xi32>
                %46 = vector.extract %arg3[0, 1, 0] : vector<1x4x4xi32>
                %47 = vector.extract %27[0] : vector<4xi32>
                %48 = arith.addi %47, %46 : i32
                %49 = vector.insertelement %48, %45[%c4 : index] : vector<16xi32>
                %50 = vector.extract %arg3[0, 1, 1] : vector<1x4x4xi32>
                %51 = vector.extract %27[1] : vector<4xi32>
                %52 = arith.addi %51, %50 : i32
                %53 = vector.insertelement %52, %49[%c5 : index] : vector<16xi32>
                %54 = vector.extract %arg3[0, 1, 2] : vector<1x4x4xi32>
                %55 = vector.extract %27[2] : vector<4xi32>
                %56 = arith.addi %55, %54 : i32
                %57 = vector.insertelement %56, %53[%c6 : index] : vector<16xi32>
                %58 = vector.extract %arg3[0, 1, 3] : vector<1x4x4xi32>
                %59 = vector.extract %27[3] : vector<4xi32>
                %60 = arith.addi %59, %58 : i32
                %61 = vector.insertelement %60, %57[%c7 : index] : vector<16xi32>
                %62 = vector.extract %arg3[0, 2, 0] : vector<1x4x4xi32>
                %63 = vector.extract %28[0] : vector<4xi32>
                %64 = arith.addi %63, %62 : i32
                %65 = vector.insertelement %64, %61[%c8 : index] : vector<16xi32>
                %66 = vector.extract %arg3[0, 2, 1] : vector<1x4x4xi32>
                %67 = vector.extract %28[1] : vector<4xi32>
                %68 = arith.addi %67, %66 : i32
                %69 = vector.insertelement %68, %65[%c9 : index] : vector<16xi32>
                %70 = vector.extract %arg3[0, 2, 2] : vector<1x4x4xi32>
                %71 = vector.extract %28[2] : vector<4xi32>
                %72 = arith.addi %71, %70 : i32
                %73 = vector.insertelement %72, %69[%c10 : index] : vector<16xi32>
                %74 = vector.extract %arg3[0, 2, 3] : vector<1x4x4xi32>
                %75 = vector.extract %28[3] : vector<4xi32>
                %76 = arith.addi %75, %74 : i32
                %77 = vector.insertelement %76, %73[%c11 : index] : vector<16xi32>
                %78 = vector.extract %arg3[0, 3, 0] : vector<1x4x4xi32>
                %79 = vector.extract %29[0] : vector<4xi32>
                %80 = arith.addi %79, %78 : i32
                %81 = vector.insertelement %80, %77[%c12 : index] : vector<16xi32>
                %82 = vector.extract %arg3[0, 3, 1] : vector<1x4x4xi32>
                %83 = vector.extract %29[1] : vector<4xi32>
                %84 = arith.addi %83, %82 : i32
                %85 = vector.insertelement %84, %81[%c13 : index] : vector<16xi32>
                %86 = vector.extract %arg3[0, 3, 2] : vector<1x4x4xi32>
                %87 = vector.extract %29[2] : vector<4xi32>
                %88 = arith.addi %87, %86 : i32
                %89 = vector.insertelement %88, %85[%c14 : index] : vector<16xi32>
                %90 = vector.extract %arg3[0, 3, 3] : vector<1x4x4xi32>
                %91 = vector.extract %29[3] : vector<4xi32>
                %92 = arith.addi %91, %90 : i32
                %93 = vector.insertelement %92, %89[%c15 : index] : vector<16xi32>
                %94 = vector.extract %93[0] : vector<16xi32>
                %95 = vector.insert %94, %cst_1 [0, 0, 0] : i32 into vector<1x4x4xi32>
                %96 = vector.extract %93[1] : vector<16xi32>
                %97 = vector.insert %96, %95 [0, 0, 1] : i32 into vector<1x4x4xi32>
                %98 = vector.extract %93[2] : vector<16xi32>
                %99 = vector.insert %98, %97 [0, 0, 2] : i32 into vector<1x4x4xi32>
                %100 = vector.extract %93[3] : vector<16xi32>
                %101 = vector.insert %100, %99 [0, 0, 3] : i32 into vector<1x4x4xi32>
                %102 = vector.extract %93[4] : vector<16xi32>
                %103 = vector.insert %102, %101 [0, 1, 0] : i32 into vector<1x4x4xi32>
                %104 = vector.extract %93[5] : vector<16xi32>
                %105 = vector.insert %104, %103 [0, 1, 1] : i32 into vector<1x4x4xi32>
                %106 = vector.extract %93[6] : vector<16xi32>
                %107 = vector.insert %106, %105 [0, 1, 2] : i32 into vector<1x4x4xi32>
                %108 = vector.extract %93[7] : vector<16xi32>
                %109 = vector.insert %108, %107 [0, 1, 3] : i32 into vector<1x4x4xi32>
                %110 = vector.extract %93[8] : vector<16xi32>
                %111 = vector.insert %110, %109 [0, 2, 0] : i32 into vector<1x4x4xi32>
                %112 = vector.extract %93[9] : vector<16xi32>
                %113 = vector.insert %112, %111 [0, 2, 1] : i32 into vector<1x4x4xi32>
                %114 = vector.extract %93[10] : vector<16xi32>
                %115 = vector.insert %114, %113 [0, 2, 2] : i32 into vector<1x4x4xi32>
                %116 = vector.extract %93[11] : vector<16xi32>
                %117 = vector.insert %116, %115 [0, 2, 3] : i32 into vector<1x4x4xi32>
                %118 = vector.extract %93[12] : vector<16xi32>
                %119 = vector.insert %118, %117 [0, 3, 0] : i32 into vector<1x4x4xi32>
                %120 = vector.extract %93[13] : vector<16xi32>
                %121 = vector.insert %120, %119 [0, 3, 1] : i32 into vector<1x4x4xi32>
                %122 = vector.extract %93[14] : vector<16xi32>
                %123 = vector.insert %122, %121 [0, 3, 2] : i32 into vector<1x4x4xi32>
                %124 = vector.extract %93[15] : vector<16xi32>
                %125 = vector.insert %124, %123 [0, 3, 3] : i32 into vector<1x4x4xi32>
                scf.yield %125 : vector<1x4x4xi32>
              }
              %9 = vector.load %4[%arg0, %arg1] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
              %10 = vector.extract %8[0, 0] : vector<1x4x4xi32>
              %11 = vector.extract %9[0] : vector<4xi32>
              %12 = vector.reduction <add>, %10, %11 : vector<4xi32> into i32
              %13 = vector.insertelement %12, %cst_0[%c0 : index] : vector<4xi32>
              %14 = vector.extract %8[0, 1] : vector<1x4x4xi32>
              %15 = vector.extract %9[1] : vector<4xi32>
              %16 = vector.reduction <add>, %14, %15 : vector<4xi32> into i32
              %17 = vector.insertelement %16, %13[%c1 : index] : vector<4xi32>
              %18 = vector.extract %8[0, 2] : vector<1x4x4xi32>
              %19 = vector.extract %9[2] : vector<4xi32>
              %20 = vector.reduction <add>, %18, %19 : vector<4xi32> into i32
              %21 = vector.insertelement %20, %17[%c2 : index] : vector<4xi32>
              %22 = vector.extract %8[0, 3] : vector<1x4x4xi32>
              %23 = vector.extract %9[3] : vector<4xi32>
              %24 = vector.reduction <add>, %22, %23 : vector<4xi32> into i32
              %25 = vector.insertelement %24, %21[%c3 : index] : vector<4xi32>
              vector.store %25, %4[%arg0, %arg1] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LLVMCPULowerExecutableTarget (iree-llvmcpu-lower-executable-target) ('hal.executable.variant' operation: @embedded_elf_x86_64) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<16xi32>
          %c5 = arith.constant 5 : index
          %c6 = arith.constant 6 : index
          %c7 = arith.constant 7 : index
          %c8 = arith.constant 8 : index
          %c9 = arith.constant 9 : index
          %c10 = arith.constant 10 : index
          %c11 = arith.constant 11 : index
          %c12 = arith.constant 12 : index
          %c13 = arith.constant 13 : index
          %c14 = arith.constant 14 : index
          %c15 = arith.constant 15 : index
          %cst_0 = arith.constant dense<0> : vector<4xi32>
          %c2 = arith.constant 2 : index
          %c3 = arith.constant 3 : index
          %cst_1 = arith.constant dense<0> : vector<1x4x4xi32>
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          scf.for %arg0 = %c0 to %c32 step %c1 {
            scf.for %arg1 = %c0 to %c32 step %c4 {
              %6 = memref.subview %5[%arg0, %arg1, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
              %7 = memref.expand_shape %6 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
              %8 = scf.for %arg2 = %c0 to %c32 step %c1 iter_args(%arg3 = %cst_1) -> (vector<1x4x4xi32>) {
                %26 = vector.load %7[%c0, %c0, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %27 = vector.load %7[%c0, %c1, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %28 = vector.load %7[%c0, %c2, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %29 = vector.load %7[%c0, %c3, %arg2, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
                %30 = vector.extract %arg3[0, 0, 0] : vector<1x4x4xi32>
                %31 = vector.extract %26[0] : vector<4xi32>
                %32 = arith.addi %31, %30 : i32
                %33 = vector.insertelement %32, %cst[%c0 : index] : vector<16xi32>
                %34 = vector.extract %arg3[0, 0, 1] : vector<1x4x4xi32>
                %35 = vector.extract %26[1] : vector<4xi32>
                %36 = arith.addi %35, %34 : i32
                %37 = vector.insertelement %36, %33[%c1 : index] : vector<16xi32>
                %38 = vector.extract %arg3[0, 0, 2] : vector<1x4x4xi32>
                %39 = vector.extract %26[2] : vector<4xi32>
                %40 = arith.addi %39, %38 : i32
                %41 = vector.insertelement %40, %37[%c2 : index] : vector<16xi32>
                %42 = vector.extract %arg3[0, 0, 3] : vector<1x4x4xi32>
                %43 = vector.extract %26[3] : vector<4xi32>
                %44 = arith.addi %43, %42 : i32
                %45 = vector.insertelement %44, %41[%c3 : index] : vector<16xi32>
                %46 = vector.extract %arg3[0, 1, 0] : vector<1x4x4xi32>
                %47 = vector.extract %27[0] : vector<4xi32>
                %48 = arith.addi %47, %46 : i32
                %49 = vector.insertelement %48, %45[%c4 : index] : vector<16xi32>
                %50 = vector.extract %arg3[0, 1, 1] : vector<1x4x4xi32>
                %51 = vector.extract %27[1] : vector<4xi32>
                %52 = arith.addi %51, %50 : i32
                %53 = vector.insertelement %52, %49[%c5 : index] : vector<16xi32>
                %54 = vector.extract %arg3[0, 1, 2] : vector<1x4x4xi32>
                %55 = vector.extract %27[2] : vector<4xi32>
                %56 = arith.addi %55, %54 : i32
                %57 = vector.insertelement %56, %53[%c6 : index] : vector<16xi32>
                %58 = vector.extract %arg3[0, 1, 3] : vector<1x4x4xi32>
                %59 = vector.extract %27[3] : vector<4xi32>
                %60 = arith.addi %59, %58 : i32
                %61 = vector.insertelement %60, %57[%c7 : index] : vector<16xi32>
                %62 = vector.extract %arg3[0, 2, 0] : vector<1x4x4xi32>
                %63 = vector.extract %28[0] : vector<4xi32>
                %64 = arith.addi %63, %62 : i32
                %65 = vector.insertelement %64, %61[%c8 : index] : vector<16xi32>
                %66 = vector.extract %arg3[0, 2, 1] : vector<1x4x4xi32>
                %67 = vector.extract %28[1] : vector<4xi32>
                %68 = arith.addi %67, %66 : i32
                %69 = vector.insertelement %68, %65[%c9 : index] : vector<16xi32>
                %70 = vector.extract %arg3[0, 2, 2] : vector<1x4x4xi32>
                %71 = vector.extract %28[2] : vector<4xi32>
                %72 = arith.addi %71, %70 : i32
                %73 = vector.insertelement %72, %69[%c10 : index] : vector<16xi32>
                %74 = vector.extract %arg3[0, 2, 3] : vector<1x4x4xi32>
                %75 = vector.extract %28[3] : vector<4xi32>
                %76 = arith.addi %75, %74 : i32
                %77 = vector.insertelement %76, %73[%c11 : index] : vector<16xi32>
                %78 = vector.extract %arg3[0, 3, 0] : vector<1x4x4xi32>
                %79 = vector.extract %29[0] : vector<4xi32>
                %80 = arith.addi %79, %78 : i32
                %81 = vector.insertelement %80, %77[%c12 : index] : vector<16xi32>
                %82 = vector.extract %arg3[0, 3, 1] : vector<1x4x4xi32>
                %83 = vector.extract %29[1] : vector<4xi32>
                %84 = arith.addi %83, %82 : i32
                %85 = vector.insertelement %84, %81[%c13 : index] : vector<16xi32>
                %86 = vector.extract %arg3[0, 3, 2] : vector<1x4x4xi32>
                %87 = vector.extract %29[2] : vector<4xi32>
                %88 = arith.addi %87, %86 : i32
                %89 = vector.insertelement %88, %85[%c14 : index] : vector<16xi32>
                %90 = vector.extract %arg3[0, 3, 3] : vector<1x4x4xi32>
                %91 = vector.extract %29[3] : vector<4xi32>
                %92 = arith.addi %91, %90 : i32
                %93 = vector.insertelement %92, %89[%c15 : index] : vector<16xi32>
                %94 = vector.extract %93[0] : vector<16xi32>
                %95 = vector.insert %94, %cst_1 [0, 0, 0] : i32 into vector<1x4x4xi32>
                %96 = vector.extract %93[1] : vector<16xi32>
                %97 = vector.insert %96, %95 [0, 0, 1] : i32 into vector<1x4x4xi32>
                %98 = vector.extract %93[2] : vector<16xi32>
                %99 = vector.insert %98, %97 [0, 0, 2] : i32 into vector<1x4x4xi32>
                %100 = vector.extract %93[3] : vector<16xi32>
                %101 = vector.insert %100, %99 [0, 0, 3] : i32 into vector<1x4x4xi32>
                %102 = vector.extract %93[4] : vector<16xi32>
                %103 = vector.insert %102, %101 [0, 1, 0] : i32 into vector<1x4x4xi32>
                %104 = vector.extract %93[5] : vector<16xi32>
                %105 = vector.insert %104, %103 [0, 1, 1] : i32 into vector<1x4x4xi32>
                %106 = vector.extract %93[6] : vector<16xi32>
                %107 = vector.insert %106, %105 [0, 1, 2] : i32 into vector<1x4x4xi32>
                %108 = vector.extract %93[7] : vector<16xi32>
                %109 = vector.insert %108, %107 [0, 1, 3] : i32 into vector<1x4x4xi32>
                %110 = vector.extract %93[8] : vector<16xi32>
                %111 = vector.insert %110, %109 [0, 2, 0] : i32 into vector<1x4x4xi32>
                %112 = vector.extract %93[9] : vector<16xi32>
                %113 = vector.insert %112, %111 [0, 2, 1] : i32 into vector<1x4x4xi32>
                %114 = vector.extract %93[10] : vector<16xi32>
                %115 = vector.insert %114, %113 [0, 2, 2] : i32 into vector<1x4x4xi32>
                %116 = vector.extract %93[11] : vector<16xi32>
                %117 = vector.insert %116, %115 [0, 2, 3] : i32 into vector<1x4x4xi32>
                %118 = vector.extract %93[12] : vector<16xi32>
                %119 = vector.insert %118, %117 [0, 3, 0] : i32 into vector<1x4x4xi32>
                %120 = vector.extract %93[13] : vector<16xi32>
                %121 = vector.insert %120, %119 [0, 3, 1] : i32 into vector<1x4x4xi32>
                %122 = vector.extract %93[14] : vector<16xi32>
                %123 = vector.insert %122, %121 [0, 3, 2] : i32 into vector<1x4x4xi32>
                %124 = vector.extract %93[15] : vector<16xi32>
                %125 = vector.insert %124, %123 [0, 3, 3] : i32 into vector<1x4x4xi32>
                scf.yield %125 : vector<1x4x4xi32>
              }
              %9 = vector.load %4[%arg0, %arg1] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
              %10 = vector.extract %8[0, 0] : vector<1x4x4xi32>
              %11 = vector.extract %9[0] : vector<4xi32>
              %12 = vector.reduction <add>, %10, %11 : vector<4xi32> into i32
              %13 = vector.insertelement %12, %cst_0[%c0 : index] : vector<4xi32>
              %14 = vector.extract %8[0, 1] : vector<1x4x4xi32>
              %15 = vector.extract %9[1] : vector<4xi32>
              %16 = vector.reduction <add>, %14, %15 : vector<4xi32> into i32
              %17 = vector.insertelement %16, %13[%c1 : index] : vector<4xi32>
              %18 = vector.extract %8[0, 2] : vector<1x4x4xi32>
              %19 = vector.extract %9[2] : vector<4xi32>
              %20 = vector.reduction <add>, %18, %19 : vector<4xi32> into i32
              %21 = vector.insertelement %20, %17[%c2 : index] : vector<4xi32>
              %22 = vector.extract %8[0, 3] : vector<1x4x4xi32>
              %23 = vector.extract %9[3] : vector<4xi32>
              %24 = vector.reduction <add>, %22, %23 : vector<4xi32> into i32
              %25 = vector.insertelement %24, %21[%c3 : index] : vector<4xi32>
              vector.store %25, %4[%arg0, %arg1] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
            }
          }
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After SCFToControlFlow (convert-scf-to-cf) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<16xi32>
          %c5 = arith.constant 5 : index
          %c6 = arith.constant 6 : index
          %c7 = arith.constant 7 : index
          %c8 = arith.constant 8 : index
          %c9 = arith.constant 9 : index
          %c10 = arith.constant 10 : index
          %c11 = arith.constant 11 : index
          %c12 = arith.constant 12 : index
          %c13 = arith.constant 13 : index
          %c14 = arith.constant 14 : index
          %c15 = arith.constant 15 : index
          %cst_0 = arith.constant dense<0> : vector<4xi32>
          %c2 = arith.constant 2 : index
          %c3 = arith.constant 3 : index
          %cst_1 = arith.constant dense<0> : vector<1x4x4xi32>
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          cf.br ^bb1(%c0 : index)
        ^bb1(%6: index):  // 2 preds: ^bb0, ^bb8
          %7 = arith.cmpi slt, %6, %c32 : index
          cf.cond_br %7, ^bb2, ^bb9
        ^bb2:  // pred: ^bb1
          cf.br ^bb3(%c0 : index)
        ^bb3(%8: index):  // 2 preds: ^bb2, ^bb7
          %9 = arith.cmpi slt, %8, %c32 : index
          cf.cond_br %9, ^bb4, ^bb8
        ^bb4:  // pred: ^bb3
          %10 = memref.subview %5[%6, %8, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
          %11 = memref.expand_shape %10 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
          cf.br ^bb5(%c0, %cst_1 : index, vector<1x4x4xi32>)
        ^bb5(%12: index, %13: vector<1x4x4xi32>):  // 2 preds: ^bb4, ^bb6
          %14 = arith.cmpi slt, %12, %c32 : index
          cf.cond_br %14, ^bb6, ^bb7
        ^bb6:  // pred: ^bb5
          %15 = vector.load %11[%c0, %c0, %12, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
          %16 = vector.load %11[%c0, %c1, %12, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
          %17 = vector.load %11[%c0, %c2, %12, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
          %18 = vector.load %11[%c0, %c3, %12, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
          %19 = vector.extract %13[0, 0, 0] : vector<1x4x4xi32>
          %20 = vector.extract %15[0] : vector<4xi32>
          %21 = arith.addi %20, %19 : i32
          %22 = vector.insertelement %21, %cst[%c0 : index] : vector<16xi32>
          %23 = vector.extract %13[0, 0, 1] : vector<1x4x4xi32>
          %24 = vector.extract %15[1] : vector<4xi32>
          %25 = arith.addi %24, %23 : i32
          %26 = vector.insertelement %25, %22[%c1 : index] : vector<16xi32>
          %27 = vector.extract %13[0, 0, 2] : vector<1x4x4xi32>
          %28 = vector.extract %15[2] : vector<4xi32>
          %29 = arith.addi %28, %27 : i32
          %30 = vector.insertelement %29, %26[%c2 : index] : vector<16xi32>
          %31 = vector.extract %13[0, 0, 3] : vector<1x4x4xi32>
          %32 = vector.extract %15[3] : vector<4xi32>
          %33 = arith.addi %32, %31 : i32
          %34 = vector.insertelement %33, %30[%c3 : index] : vector<16xi32>
          %35 = vector.extract %13[0, 1, 0] : vector<1x4x4xi32>
          %36 = vector.extract %16[0] : vector<4xi32>
          %37 = arith.addi %36, %35 : i32
          %38 = vector.insertelement %37, %34[%c4 : index] : vector<16xi32>
          %39 = vector.extract %13[0, 1, 1] : vector<1x4x4xi32>
          %40 = vector.extract %16[1] : vector<4xi32>
          %41 = arith.addi %40, %39 : i32
          %42 = vector.insertelement %41, %38[%c5 : index] : vector<16xi32>
          %43 = vector.extract %13[0, 1, 2] : vector<1x4x4xi32>
          %44 = vector.extract %16[2] : vector<4xi32>
          %45 = arith.addi %44, %43 : i32
          %46 = vector.insertelement %45, %42[%c6 : index] : vector<16xi32>
          %47 = vector.extract %13[0, 1, 3] : vector<1x4x4xi32>
          %48 = vector.extract %16[3] : vector<4xi32>
          %49 = arith.addi %48, %47 : i32
          %50 = vector.insertelement %49, %46[%c7 : index] : vector<16xi32>
          %51 = vector.extract %13[0, 2, 0] : vector<1x4x4xi32>
          %52 = vector.extract %17[0] : vector<4xi32>
          %53 = arith.addi %52, %51 : i32
          %54 = vector.insertelement %53, %50[%c8 : index] : vector<16xi32>
          %55 = vector.extract %13[0, 2, 1] : vector<1x4x4xi32>
          %56 = vector.extract %17[1] : vector<4xi32>
          %57 = arith.addi %56, %55 : i32
          %58 = vector.insertelement %57, %54[%c9 : index] : vector<16xi32>
          %59 = vector.extract %13[0, 2, 2] : vector<1x4x4xi32>
          %60 = vector.extract %17[2] : vector<4xi32>
          %61 = arith.addi %60, %59 : i32
          %62 = vector.insertelement %61, %58[%c10 : index] : vector<16xi32>
          %63 = vector.extract %13[0, 2, 3] : vector<1x4x4xi32>
          %64 = vector.extract %17[3] : vector<4xi32>
          %65 = arith.addi %64, %63 : i32
          %66 = vector.insertelement %65, %62[%c11 : index] : vector<16xi32>
          %67 = vector.extract %13[0, 3, 0] : vector<1x4x4xi32>
          %68 = vector.extract %18[0] : vector<4xi32>
          %69 = arith.addi %68, %67 : i32
          %70 = vector.insertelement %69, %66[%c12 : index] : vector<16xi32>
          %71 = vector.extract %13[0, 3, 1] : vector<1x4x4xi32>
          %72 = vector.extract %18[1] : vector<4xi32>
          %73 = arith.addi %72, %71 : i32
          %74 = vector.insertelement %73, %70[%c13 : index] : vector<16xi32>
          %75 = vector.extract %13[0, 3, 2] : vector<1x4x4xi32>
          %76 = vector.extract %18[2] : vector<4xi32>
          %77 = arith.addi %76, %75 : i32
          %78 = vector.insertelement %77, %74[%c14 : index] : vector<16xi32>
          %79 = vector.extract %13[0, 3, 3] : vector<1x4x4xi32>
          %80 = vector.extract %18[3] : vector<4xi32>
          %81 = arith.addi %80, %79 : i32
          %82 = vector.insertelement %81, %78[%c15 : index] : vector<16xi32>
          %83 = vector.extract %82[0] : vector<16xi32>
          %84 = vector.insert %83, %cst_1 [0, 0, 0] : i32 into vector<1x4x4xi32>
          %85 = vector.extract %82[1] : vector<16xi32>
          %86 = vector.insert %85, %84 [0, 0, 1] : i32 into vector<1x4x4xi32>
          %87 = vector.extract %82[2] : vector<16xi32>
          %88 = vector.insert %87, %86 [0, 0, 2] : i32 into vector<1x4x4xi32>
          %89 = vector.extract %82[3] : vector<16xi32>
          %90 = vector.insert %89, %88 [0, 0, 3] : i32 into vector<1x4x4xi32>
          %91 = vector.extract %82[4] : vector<16xi32>
          %92 = vector.insert %91, %90 [0, 1, 0] : i32 into vector<1x4x4xi32>
          %93 = vector.extract %82[5] : vector<16xi32>
          %94 = vector.insert %93, %92 [0, 1, 1] : i32 into vector<1x4x4xi32>
          %95 = vector.extract %82[6] : vector<16xi32>
          %96 = vector.insert %95, %94 [0, 1, 2] : i32 into vector<1x4x4xi32>
          %97 = vector.extract %82[7] : vector<16xi32>
          %98 = vector.insert %97, %96 [0, 1, 3] : i32 into vector<1x4x4xi32>
          %99 = vector.extract %82[8] : vector<16xi32>
          %100 = vector.insert %99, %98 [0, 2, 0] : i32 into vector<1x4x4xi32>
          %101 = vector.extract %82[9] : vector<16xi32>
          %102 = vector.insert %101, %100 [0, 2, 1] : i32 into vector<1x4x4xi32>
          %103 = vector.extract %82[10] : vector<16xi32>
          %104 = vector.insert %103, %102 [0, 2, 2] : i32 into vector<1x4x4xi32>
          %105 = vector.extract %82[11] : vector<16xi32>
          %106 = vector.insert %105, %104 [0, 2, 3] : i32 into vector<1x4x4xi32>
          %107 = vector.extract %82[12] : vector<16xi32>
          %108 = vector.insert %107, %106 [0, 3, 0] : i32 into vector<1x4x4xi32>
          %109 = vector.extract %82[13] : vector<16xi32>
          %110 = vector.insert %109, %108 [0, 3, 1] : i32 into vector<1x4x4xi32>
          %111 = vector.extract %82[14] : vector<16xi32>
          %112 = vector.insert %111, %110 [0, 3, 2] : i32 into vector<1x4x4xi32>
          %113 = vector.extract %82[15] : vector<16xi32>
          %114 = vector.insert %113, %112 [0, 3, 3] : i32 into vector<1x4x4xi32>
          %115 = arith.addi %12, %c1 : index
          cf.br ^bb5(%115, %114 : index, vector<1x4x4xi32>)
        ^bb7:  // pred: ^bb5
          %116 = vector.load %4[%6, %8] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
          %117 = vector.extract %13[0, 0] : vector<1x4x4xi32>
          %118 = vector.extract %116[0] : vector<4xi32>
          %119 = vector.reduction <add>, %117, %118 : vector<4xi32> into i32
          %120 = vector.insertelement %119, %cst_0[%c0 : index] : vector<4xi32>
          %121 = vector.extract %13[0, 1] : vector<1x4x4xi32>
          %122 = vector.extract %116[1] : vector<4xi32>
          %123 = vector.reduction <add>, %121, %122 : vector<4xi32> into i32
          %124 = vector.insertelement %123, %120[%c1 : index] : vector<4xi32>
          %125 = vector.extract %13[0, 2] : vector<1x4x4xi32>
          %126 = vector.extract %116[2] : vector<4xi32>
          %127 = vector.reduction <add>, %125, %126 : vector<4xi32> into i32
          %128 = vector.insertelement %127, %124[%c2 : index] : vector<4xi32>
          %129 = vector.extract %13[0, 3] : vector<1x4x4xi32>
          %130 = vector.extract %116[3] : vector<4xi32>
          %131 = vector.reduction <add>, %129, %130 : vector<4xi32> into i32
          %132 = vector.insertelement %131, %128[%c3 : index] : vector<4xi32>
          vector.store %132, %4[%6, %8] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
          %133 = arith.addi %8, %c4 : index
          cf.br ^bb3(%133 : index)
        ^bb8:  // pred: ^bb3
          %134 = arith.addi %6, %c1 : index
          cf.br ^bb1(%134 : index)
        ^bb9:  // pred: ^bb1
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('func.func' operation: @_split_reduction_pass2_dispatch_0_generic_512x256x128) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#map = affine_map<()[s0] -> (s0 * 32)>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module {
        func.func @_split_reduction_pass2_dispatch_0_generic_512x256x128() {
          %cst = arith.constant dense<0> : vector<16xi32>
          %c5 = arith.constant 5 : index
          %c6 = arith.constant 6 : index
          %c7 = arith.constant 7 : index
          %c8 = arith.constant 8 : index
          %c9 = arith.constant 9 : index
          %c10 = arith.constant 10 : index
          %c11 = arith.constant 11 : index
          %c12 = arith.constant 12 : index
          %c13 = arith.constant 13 : index
          %c14 = arith.constant 14 : index
          %c15 = arith.constant 15 : index
          %cst_0 = arith.constant dense<0> : vector<4xi32>
          %c2 = arith.constant 2 : index
          %c3 = arith.constant 3 : index
          %cst_1 = arith.constant dense<0> : vector<1x4x4xi32>
          %c4 = arith.constant 4 : index
          %c1 = arith.constant 1 : index
          %c32 = arith.constant 32 : index
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256x128xi32>
          memref.assume_alignment %0, 64 : memref<512x256x128xi32>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) offset(%c0) alignment(64) : memref<512x256xi32>
          memref.assume_alignment %1, 64 : memref<512x256xi32>
          %workgroup_id_x = hal.interface.workgroup.id[0] : index
          %workgroup_id_y = hal.interface.workgroup.id[1] : index
          %2 = affine.apply #map()[%workgroup_id_y]
          %3 = affine.apply #map()[%workgroup_id_x]
          %4 = memref.subview %1[%2, %3] [32, 32] [1, 1] : memref<512x256xi32> to memref<32x32xi32, strided<[256, 1], offset: ?>>
          %5 = memref.subview %0[%2, %3, 0] [32, 32, 128] [1, 1, 1] : memref<512x256x128xi32> to memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>>
          cf.br ^bb1(%c0 : index)
        ^bb1(%6: index):  // 2 preds: ^bb0, ^bb7
          %7 = arith.cmpi slt, %6, %c32 : index
          cf.cond_br %7, ^bb2(%c0 : index), ^bb8
        ^bb2(%8: index):  // 2 preds: ^bb1, ^bb6
          %9 = arith.cmpi slt, %8, %c32 : index
          cf.cond_br %9, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %10 = memref.subview %5[%6, %8, 0] [1, 4, 128] [1, 1, 1] : memref<32x32x128xi32, strided<[32768, 128, 1], offset: ?>> to memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>>
          %11 = memref.expand_shape %10 [[0], [1], [2, 3]] : memref<1x4x128xi32, strided<[32768, 128, 1], offset: ?>> into memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>
          cf.br ^bb4(%c0, %cst_1 : index, vector<1x4x4xi32>)
        ^bb4(%12: index, %13: vector<1x4x4xi32>):  // 2 preds: ^bb3, ^bb5
          %14 = arith.cmpi slt, %12, %c32 : index
          cf.cond_br %14, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %15 = vector.load %11[%c0, %c0, %12, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
          %16 = vector.load %11[%c0, %c1, %12, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
          %17 = vector.load %11[%c0, %c2, %12, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
          %18 = vector.load %11[%c0, %c3, %12, %c0] : memref<1x4x32x4xi32, strided<[32768, 128, 4, 1], offset: ?>>, vector<4xi32>
          %19 = vector.extract %13[0, 0, 0] : vector<1x4x4xi32>
          %20 = vector.extract %15[0] : vector<4xi32>
          %21 = arith.addi %20, %19 : i32
          %22 = vector.insertelement %21, %cst[%c0 : index] : vector<16xi32>
          %23 = vector.extract %13[0, 0, 1] : vector<1x4x4xi32>
          %24 = vector.extract %15[1] : vector<4xi32>
          %25 = arith.addi %24, %23 : i32
          %26 = vector.insertelement %25, %22[%c1 : index] : vector<16xi32>
          %27 = vector.extract %13[0, 0, 2] : vector<1x4x4xi32>
          %28 = vector.extract %15[2] : vector<4xi32>
          %29 = arith.addi %28, %27 : i32
          %30 = vector.insertelement %29, %26[%c2 : index] : vector<16xi32>
          %31 = vector.extract %13[0, 0, 3] : vector<1x4x4xi32>
          %32 = vector.extract %15[3] : vector<4xi32>
          %33 = arith.addi %32, %31 : i32
          %34 = vector.insertelement %33, %30[%c3 : index] : vector<16xi32>
          %35 = vector.extract %13[0, 1, 0] : vector<1x4x4xi32>
          %36 = vector.extract %16[0] : vector<4xi32>
          %37 = arith.addi %36, %35 : i32
          %38 = vector.insertelement %37, %34[%c4 : index] : vector<16xi32>
          %39 = vector.extract %13[0, 1, 1] : vector<1x4x4xi32>
          %40 = vector.extract %16[1] : vector<4xi32>
          %41 = arith.addi %40, %39 : i32
          %42 = vector.insertelement %41, %38[%c5 : index] : vector<16xi32>
          %43 = vector.extract %13[0, 1, 2] : vector<1x4x4xi32>
          %44 = vector.extract %16[2] : vector<4xi32>
          %45 = arith.addi %44, %43 : i32
          %46 = vector.insertelement %45, %42[%c6 : index] : vector<16xi32>
          %47 = vector.extract %13[0, 1, 3] : vector<1x4x4xi32>
          %48 = vector.extract %16[3] : vector<4xi32>
          %49 = arith.addi %48, %47 : i32
          %50 = vector.insertelement %49, %46[%c7 : index] : vector<16xi32>
          %51 = vector.extract %13[0, 2, 0] : vector<1x4x4xi32>
          %52 = vector.extract %17[0] : vector<4xi32>
          %53 = arith.addi %52, %51 : i32
          %54 = vector.insertelement %53, %50[%c8 : index] : vector<16xi32>
          %55 = vector.extract %13[0, 2, 1] : vector<1x4x4xi32>
          %56 = vector.extract %17[1] : vector<4xi32>
          %57 = arith.addi %56, %55 : i32
          %58 = vector.insertelement %57, %54[%c9 : index] : vector<16xi32>
          %59 = vector.extract %13[0, 2, 2] : vector<1x4x4xi32>
          %60 = vector.extract %17[2] : vector<4xi32>
          %61 = arith.addi %60, %59 : i32
          %62 = vector.insertelement %61, %58[%c10 : index] : vector<16xi32>
          %63 = vector.extract %13[0, 2, 3] : vector<1x4x4xi32>
          %64 = vector.extract %17[3] : vector<4xi32>
          %65 = arith.addi %64, %63 : i32
          %66 = vector.insertelement %65, %62[%c11 : index] : vector<16xi32>
          %67 = vector.extract %13[0, 3, 0] : vector<1x4x4xi32>
          %68 = vector.extract %18[0] : vector<4xi32>
          %69 = arith.addi %68, %67 : i32
          %70 = vector.insertelement %69, %66[%c12 : index] : vector<16xi32>
          %71 = vector.extract %13[0, 3, 1] : vector<1x4x4xi32>
          %72 = vector.extract %18[1] : vector<4xi32>
          %73 = arith.addi %72, %71 : i32
          %74 = vector.insertelement %73, %70[%c13 : index] : vector<16xi32>
          %75 = vector.extract %13[0, 3, 2] : vector<1x4x4xi32>
          %76 = vector.extract %18[2] : vector<4xi32>
          %77 = arith.addi %76, %75 : i32
          %78 = vector.insertelement %77, %74[%c14 : index] : vector<16xi32>
          %79 = vector.extract %13[0, 3, 3] : vector<1x4x4xi32>
          %80 = vector.extract %18[3] : vector<4xi32>
          %81 = arith.addi %80, %79 : i32
          %82 = vector.insertelement %81, %78[%c15 : index] : vector<16xi32>
          %83 = vector.extract %82[0] : vector<16xi32>
          %84 = vector.insert %83, %cst_1 [0, 0, 0] : i32 into vector<1x4x4xi32>
          %85 = vector.extract %82[1] : vector<16xi32>
          %86 = vector.insert %85, %84 [0, 0, 1] : i32 into vector<1x4x4xi32>
          %87 = vector.extract %82[2] : vector<16xi32>
          %88 = vector.insert %87, %86 [0, 0, 2] : i32 into vector<1x4x4xi32>
          %89 = vector.extract %82[3] : vector<16xi32>
          %90 = vector.insert %89, %88 [0, 0, 3] : i32 into vector<1x4x4xi32>
          %91 = vector.extract %82[4] : vector<16xi32>
          %92 = vector.insert %91, %90 [0, 1, 0] : i32 into vector<1x4x4xi32>
          %93 = vector.extract %82[5] : vector<16xi32>
          %94 = vector.insert %93, %92 [0, 1, 1] : i32 into vector<1x4x4xi32>
          %95 = vector.extract %82[6] : vector<16xi32>
          %96 = vector.insert %95, %94 [0, 1, 2] : i32 into vector<1x4x4xi32>
          %97 = vector.extract %82[7] : vector<16xi32>
          %98 = vector.insert %97, %96 [0, 1, 3] : i32 into vector<1x4x4xi32>
          %99 = vector.extract %82[8] : vector<16xi32>
          %100 = vector.insert %99, %98 [0, 2, 0] : i32 into vector<1x4x4xi32>
          %101 = vector.extract %82[9] : vector<16xi32>
          %102 = vector.insert %101, %100 [0, 2, 1] : i32 into vector<1x4x4xi32>
          %103 = vector.extract %82[10] : vector<16xi32>
          %104 = vector.insert %103, %102 [0, 2, 2] : i32 into vector<1x4x4xi32>
          %105 = vector.extract %82[11] : vector<16xi32>
          %106 = vector.insert %105, %104 [0, 2, 3] : i32 into vector<1x4x4xi32>
          %107 = vector.extract %82[12] : vector<16xi32>
          %108 = vector.insert %107, %106 [0, 3, 0] : i32 into vector<1x4x4xi32>
          %109 = vector.extract %82[13] : vector<16xi32>
          %110 = vector.insert %109, %108 [0, 3, 1] : i32 into vector<1x4x4xi32>
          %111 = vector.extract %82[14] : vector<16xi32>
          %112 = vector.insert %111, %110 [0, 3, 2] : i32 into vector<1x4x4xi32>
          %113 = vector.extract %82[15] : vector<16xi32>
          %114 = vector.insert %113, %112 [0, 3, 3] : i32 into vector<1x4x4xi32>
          %115 = arith.addi %12, %c1 : index
          cf.br ^bb4(%115, %114 : index, vector<1x4x4xi32>)
        ^bb6:  // pred: ^bb4
          %116 = vector.load %4[%6, %8] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
          %117 = vector.extract %13[0, 0] : vector<1x4x4xi32>
          %118 = vector.extract %116[0] : vector<4xi32>
          %119 = vector.reduction <add>, %117, %118 : vector<4xi32> into i32
          %120 = vector.insertelement %119, %cst_0[%c0 : index] : vector<4xi32>
          %121 = vector.extract %13[0, 1] : vector<1x4x4xi32>
          %122 = vector.extract %116[1] : vector<4xi32>
          %123 = vector.reduction <add>, %121, %122 : vector<4xi32> into i32
          %124 = vector.insertelement %123, %120[%c1 : index] : vector<4xi32>
          %125 = vector.extract %13[0, 2] : vector<1x4x4xi32>
          %126 = vector.extract %116[2] : vector<4xi32>
          %127 = vector.reduction <add>, %125, %126 : vector<4xi32> into i32
          %128 = vector.insertelement %127, %124[%c2 : index] : vector<4xi32>
          %129 = vector.extract %13[0, 3] : vector<1x4x4xi32>
          %130 = vector.extract %116[3] : vector<4xi32>
          %131 = vector.reduction <add>, %129, %130 : vector<4xi32> into i32
          %132 = vector.insertelement %131, %128[%c3 : index] : vector<4xi32>
          vector.store %132, %4[%6, %8] : memref<32x32xi32, strided<[256, 1], offset: ?>>, vector<4xi32>
          %133 = arith.addi %8, %c4 : index
          cf.br ^bb2(%133 : index)
        ^bb7:  // pred: ^bb2
          %134 = arith.addi %6, %c1 : index
          cf.br ^bb1(%134 : index)
        ^bb8:  // pred: ^bb1
          return
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After ConvertToLLVM (iree-convert-to-llvm) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 {
          %0 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %1 = llvm.mlir.constant(5 : index) : i64
          %2 = llvm.mlir.constant(6 : index) : i64
          %3 = llvm.mlir.constant(7 : index) : i64
          %4 = llvm.mlir.constant(8 : index) : i64
          %5 = llvm.mlir.constant(9 : index) : i64
          %6 = llvm.mlir.constant(10 : index) : i64
          %7 = llvm.mlir.constant(11 : index) : i64
          %8 = llvm.mlir.constant(12 : index) : i64
          %9 = llvm.mlir.constant(13 : index) : i64
          %10 = llvm.mlir.constant(14 : index) : i64
          %11 = llvm.mlir.constant(15 : index) : i64
          %12 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %13 = llvm.mlir.constant(2 : index) : i64
          %14 = llvm.mlir.constant(3 : index) : i64
          %15 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %16 = llvm.mlir.constant(4 : index) : i64
          %17 = llvm.mlir.constant(1 : index) : i64
          %18 = llvm.mlir.constant(32 : index) : i64
          %19 = llvm.mlir.constant(0 : index) : i64
          %20 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %21 = llvm.extractvalue %20[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.load %21 : !llvm.ptr<ptr<i8>>
          %24 = llvm.bitcast %23 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %25 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)>
          %26 = llvm.insertvalue %24, %25[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %27 = llvm.insertvalue %24, %26[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %28 = llvm.mlir.constant(0 : index) : i64
          %29 = llvm.insertvalue %28, %27[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %30 = llvm.mlir.constant(512 : index) : i64
          %31 = llvm.insertvalue %30, %29[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %32 = llvm.mlir.constant(32768 : index) : i64
          %33 = llvm.insertvalue %32, %31[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %34 = llvm.mlir.constant(256 : index) : i64
          %35 = llvm.insertvalue %34, %33[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %36 = llvm.mlir.constant(128 : index) : i64
          %37 = llvm.insertvalue %36, %35[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %38 = llvm.mlir.constant(128 : index) : i64
          %39 = llvm.insertvalue %38, %37[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.insertvalue %40, %39[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %42 = llvm.extractvalue %41[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %43 = llvm.mlir.constant(0 : index) : i64
          %44 = llvm.mlir.constant(63 : index) : i64
          %45 = llvm.ptrtoint %42 : !llvm.ptr<i32> to i64
          %46 = llvm.and %45, %44  : i64
          %47 = llvm.icmp "eq" %46, %43 : i64
          "llvm.intr.assume"(%47) : (i1) -> ()
          %48 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %49 = llvm.extractvalue %48[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %50 = llvm.mlir.constant(1 : i64) : i64
          %51 = llvm.getelementptr %49[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %52 = llvm.load %51 : !llvm.ptr<ptr<i8>>
          %53 = llvm.bitcast %52 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %54 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)>
          %55 = llvm.insertvalue %53, %54[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %56 = llvm.insertvalue %53, %55[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %57 = llvm.mlir.constant(0 : index) : i64
          %58 = llvm.insertvalue %57, %56[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %59 = llvm.mlir.constant(512 : index) : i64
          %60 = llvm.insertvalue %59, %58[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %61 = llvm.mlir.constant(256 : index) : i64
          %62 = llvm.insertvalue %61, %60[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %63 = llvm.mlir.constant(256 : index) : i64
          %64 = llvm.insertvalue %63, %62[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %65 = llvm.mlir.constant(1 : index) : i64
          %66 = llvm.insertvalue %65, %64[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %67 = llvm.extractvalue %66[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %68 = llvm.mlir.constant(0 : index) : i64
          %69 = llvm.mlir.constant(63 : index) : i64
          %70 = llvm.ptrtoint %67 : !llvm.ptr<i32> to i64
          %71 = llvm.and %70, %69  : i64
          %72 = llvm.icmp "eq" %71, %68 : i64
          "llvm.intr.assume"(%72) : (i1) -> ()
          %73 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %74 = llvm.extractvalue %73[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %75 = llvm.zext %74 : i32 to i64
          %76 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %77 = llvm.extractvalue %76[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %78 = llvm.zext %77 : i32 to i64
          %79 = llvm.mlir.constant(32 : index) : i64
          %80 = llvm.mul %78, %79  : i64
          %81 = llvm.mlir.constant(32 : index) : i64
          %82 = llvm.mul %75, %81  : i64
          %83 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)>
          %84 = llvm.extractvalue %66[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %85 = llvm.bitcast %84 : !llvm.ptr<i32> to !llvm.ptr<i32>
          %86 = llvm.insertvalue %85, %83[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %87 = llvm.extractvalue %66[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %88 = llvm.bitcast %87 : !llvm.ptr<i32> to !llvm.ptr<i32>
          %89 = llvm.insertvalue %88, %86[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %90 = llvm.extractvalue %66[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %91 = llvm.extractvalue %66[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %92 = llvm.extractvalue %66[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %93 = llvm.mul %80, %90  : i64
          %94 = llvm.add %92, %93  : i64
          %95 = llvm.mul %82, %91  : i64
          %96 = llvm.add %94, %95  : i64
          %97 = llvm.insertvalue %96, %89[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %98 = llvm.mlir.constant(32 : i64) : i64
          %99 = llvm.mlir.constant(1 : i64) : i64
          %100 = llvm.insertvalue %98, %97[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %101 = llvm.insertvalue %99, %100[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %102 = llvm.mlir.constant(32 : i64) : i64
          %103 = llvm.mlir.constant(256 : i64) : i64
          %104 = llvm.insertvalue %102, %101[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %105 = llvm.insertvalue %103, %104[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %106 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)>
          %107 = llvm.extractvalue %41[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %108 = llvm.bitcast %107 : !llvm.ptr<i32> to !llvm.ptr<i32>
          %109 = llvm.insertvalue %108, %106[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %110 = llvm.extractvalue %41[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %111 = llvm.bitcast %110 : !llvm.ptr<i32> to !llvm.ptr<i32>
          %112 = llvm.insertvalue %111, %109[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %113 = llvm.extractvalue %41[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %114 = llvm.extractvalue %41[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %115 = llvm.extractvalue %41[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %116 = llvm.extractvalue %41[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %117 = llvm.mul %80, %113  : i64
          %118 = llvm.add %116, %117  : i64
          %119 = llvm.mul %82, %114  : i64
          %120 = llvm.add %118, %119  : i64
          %121 = llvm.mlir.constant(0 : i64) : i64
          %122 = llvm.mul %121, %115  : i64
          %123 = llvm.add %120, %122  : i64
          %124 = llvm.insertvalue %123, %112[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %125 = llvm.mlir.constant(128 : i64) : i64
          %126 = llvm.mlir.constant(1 : i64) : i64
          %127 = llvm.insertvalue %125, %124[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %128 = llvm.insertvalue %126, %127[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %129 = llvm.mlir.constant(32 : i64) : i64
          %130 = llvm.mlir.constant(128 : i64) : i64
          %131 = llvm.insertvalue %129, %128[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %132 = llvm.insertvalue %130, %131[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %133 = llvm.mlir.constant(32 : i64) : i64
          %134 = llvm.mlir.constant(32768 : i64) : i64
          %135 = llvm.insertvalue %133, %132[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %136 = llvm.insertvalue %134, %135[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          llvm.br ^bb1(%19 : i64)
        ^bb1(%137: i64):  // 2 preds: ^bb0, ^bb7
          %138 = llvm.icmp "slt" %137, %18 : i64
          llvm.cond_br %138, ^bb2(%19 : i64), ^bb8
        ^bb2(%139: i64):  // 2 preds: ^bb1, ^bb6
          %140 = llvm.icmp "slt" %139, %18 : i64
          llvm.cond_br %140, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %141 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)>
          %142 = llvm.extractvalue %136[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %143 = llvm.bitcast %142 : !llvm.ptr<i32> to !llvm.ptr<i32>
          %144 = llvm.insertvalue %143, %141[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %145 = llvm.extractvalue %136[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %146 = llvm.bitcast %145 : !llvm.ptr<i32> to !llvm.ptr<i32>
          %147 = llvm.insertvalue %146, %144[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %148 = llvm.extractvalue %136[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %149 = llvm.extractvalue %136[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %150 = llvm.extractvalue %136[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %151 = llvm.extractvalue %136[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %152 = llvm.mul %137, %148  : i64
          %153 = llvm.add %151, %152  : i64
          %154 = llvm.mul %139, %149  : i64
          %155 = llvm.add %153, %154  : i64
          %156 = llvm.mlir.constant(0 : i64) : i64
          %157 = llvm.mul %156, %150  : i64
          %158 = llvm.add %155, %157  : i64
          %159 = llvm.insertvalue %158, %147[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %160 = llvm.mlir.constant(128 : i64) : i64
          %161 = llvm.mlir.constant(1 : i64) : i64
          %162 = llvm.insertvalue %160, %159[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %163 = llvm.insertvalue %161, %162[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %164 = llvm.mlir.constant(4 : i64) : i64
          %165 = llvm.mlir.constant(128 : i64) : i64
          %166 = llvm.insertvalue %164, %163[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %167 = llvm.insertvalue %165, %166[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %168 = llvm.mlir.constant(1 : i64) : i64
          %169 = llvm.mlir.constant(32768 : i64) : i64
          %170 = llvm.insertvalue %168, %167[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %171 = llvm.insertvalue %169, %170[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %172 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)>
          %173 = llvm.extractvalue %171[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %174 = llvm.insertvalue %173, %172[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %175 = llvm.extractvalue %171[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %176 = llvm.insertvalue %175, %174[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %177 = llvm.extractvalue %171[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %178 = llvm.insertvalue %177, %176[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %179 = llvm.mlir.constant(1 : index) : i64
          %180 = llvm.mlir.constant(4 : index) : i64
          %181 = llvm.mlir.constant(32 : index) : i64
          %182 = llvm.mlir.constant(4 : index) : i64
          %183 = llvm.insertvalue %179, %178[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %184 = llvm.insertvalue %180, %183[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %185 = llvm.insertvalue %181, %184[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %186 = llvm.insertvalue %182, %185[3, 3] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %187 = llvm.mlir.constant(32768 : index) : i64
          %188 = llvm.insertvalue %187, %186[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %189 = llvm.mlir.constant(128 : index) : i64
          %190 = llvm.insertvalue %189, %188[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %191 = llvm.mlir.constant(4 : index) : i64
          %192 = llvm.insertvalue %191, %190[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %193 = llvm.mlir.constant(1 : index) : i64
          %194 = llvm.insertvalue %193, %192[4, 3] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          llvm.br ^bb4(%19, %15 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%195: i64, %196: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %197 = llvm.icmp "slt" %195, %18 : i64
          llvm.cond_br %197, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %198 = llvm.extractvalue %194[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %199 = llvm.extractvalue %194[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %200 = llvm.mlir.constant(32768 : index) : i64
          %201 = llvm.mul %19, %200  : i64
          %202 = llvm.add %199, %201  : i64
          %203 = llvm.mlir.constant(128 : index) : i64
          %204 = llvm.mul %19, %203  : i64
          %205 = llvm.add %202, %204  : i64
          %206 = llvm.mlir.constant(4 : index) : i64
          %207 = llvm.mul %195, %206  : i64
          %208 = llvm.add %205, %207  : i64
          %209 = llvm.add %208, %19  : i64
          %210 = llvm.getelementptr %198[%209] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %211 = llvm.bitcast %210 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %212 = llvm.load %211 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %213 = llvm.extractvalue %194[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %214 = llvm.extractvalue %194[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %215 = llvm.mlir.constant(32768 : index) : i64
          %216 = llvm.mul %19, %215  : i64
          %217 = llvm.add %214, %216  : i64
          %218 = llvm.mlir.constant(128 : index) : i64
          %219 = llvm.mul %17, %218  : i64
          %220 = llvm.add %217, %219  : i64
          %221 = llvm.mlir.constant(4 : index) : i64
          %222 = llvm.mul %195, %221  : i64
          %223 = llvm.add %220, %222  : i64
          %224 = llvm.add %223, %19  : i64
          %225 = llvm.getelementptr %213[%224] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %226 = llvm.bitcast %225 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %227 = llvm.load %226 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %228 = llvm.extractvalue %194[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %229 = llvm.extractvalue %194[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %230 = llvm.mlir.constant(32768 : index) : i64
          %231 = llvm.mul %19, %230  : i64
          %232 = llvm.add %229, %231  : i64
          %233 = llvm.mlir.constant(128 : index) : i64
          %234 = llvm.mul %13, %233  : i64
          %235 = llvm.add %232, %234  : i64
          %236 = llvm.mlir.constant(4 : index) : i64
          %237 = llvm.mul %195, %236  : i64
          %238 = llvm.add %235, %237  : i64
          %239 = llvm.add %238, %19  : i64
          %240 = llvm.getelementptr %228[%239] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %241 = llvm.bitcast %240 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %242 = llvm.load %241 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %243 = llvm.extractvalue %194[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %244 = llvm.extractvalue %194[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %245 = llvm.mlir.constant(32768 : index) : i64
          %246 = llvm.mul %19, %245  : i64
          %247 = llvm.add %244, %246  : i64
          %248 = llvm.mlir.constant(128 : index) : i64
          %249 = llvm.mul %14, %248  : i64
          %250 = llvm.add %247, %249  : i64
          %251 = llvm.mlir.constant(4 : index) : i64
          %252 = llvm.mul %195, %251  : i64
          %253 = llvm.add %250, %252  : i64
          %254 = llvm.add %253, %19  : i64
          %255 = llvm.getelementptr %243[%254] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %256 = llvm.bitcast %255 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %257 = llvm.load %256 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %258 = llvm.extractvalue %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %259 = llvm.mlir.constant(0 : i64) : i64
          %260 = llvm.extractelement %258[%259 : i64] : vector<4xi32>
          %261 = llvm.mlir.constant(0 : i64) : i64
          %262 = llvm.extractelement %212[%261 : i64] : vector<4xi32>
          %263 = llvm.add %262, %260  : i32
          %264 = llvm.insertelement %263, %0[%19 : i64] : vector<16xi32>
          %265 = llvm.extractvalue %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %266 = llvm.mlir.constant(1 : i64) : i64
          %267 = llvm.extractelement %265[%266 : i64] : vector<4xi32>
          %268 = llvm.mlir.constant(1 : i64) : i64
          %269 = llvm.extractelement %212[%268 : i64] : vector<4xi32>
          %270 = llvm.add %269, %267  : i32
          %271 = llvm.insertelement %270, %264[%17 : i64] : vector<16xi32>
          %272 = llvm.extractvalue %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %273 = llvm.mlir.constant(2 : i64) : i64
          %274 = llvm.extractelement %272[%273 : i64] : vector<4xi32>
          %275 = llvm.mlir.constant(2 : i64) : i64
          %276 = llvm.extractelement %212[%275 : i64] : vector<4xi32>
          %277 = llvm.add %276, %274  : i32
          %278 = llvm.insertelement %277, %271[%13 : i64] : vector<16xi32>
          %279 = llvm.extractvalue %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %280 = llvm.mlir.constant(3 : i64) : i64
          %281 = llvm.extractelement %279[%280 : i64] : vector<4xi32>
          %282 = llvm.mlir.constant(3 : i64) : i64
          %283 = llvm.extractelement %212[%282 : i64] : vector<4xi32>
          %284 = llvm.add %283, %281  : i32
          %285 = llvm.insertelement %284, %278[%14 : i64] : vector<16xi32>
          %286 = llvm.extractvalue %196[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %287 = llvm.mlir.constant(0 : i64) : i64
          %288 = llvm.extractelement %286[%287 : i64] : vector<4xi32>
          %289 = llvm.mlir.constant(0 : i64) : i64
          %290 = llvm.extractelement %227[%289 : i64] : vector<4xi32>
          %291 = llvm.add %290, %288  : i32
          %292 = llvm.insertelement %291, %285[%16 : i64] : vector<16xi32>
          %293 = llvm.extractvalue %196[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %294 = llvm.mlir.constant(1 : i64) : i64
          %295 = llvm.extractelement %293[%294 : i64] : vector<4xi32>
          %296 = llvm.mlir.constant(1 : i64) : i64
          %297 = llvm.extractelement %227[%296 : i64] : vector<4xi32>
          %298 = llvm.add %297, %295  : i32
          %299 = llvm.insertelement %298, %292[%1 : i64] : vector<16xi32>
          %300 = llvm.extractvalue %196[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %301 = llvm.mlir.constant(2 : i64) : i64
          %302 = llvm.extractelement %300[%301 : i64] : vector<4xi32>
          %303 = llvm.mlir.constant(2 : i64) : i64
          %304 = llvm.extractelement %227[%303 : i64] : vector<4xi32>
          %305 = llvm.add %304, %302  : i32
          %306 = llvm.insertelement %305, %299[%2 : i64] : vector<16xi32>
          %307 = llvm.extractvalue %196[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %308 = llvm.mlir.constant(3 : i64) : i64
          %309 = llvm.extractelement %307[%308 : i64] : vector<4xi32>
          %310 = llvm.mlir.constant(3 : i64) : i64
          %311 = llvm.extractelement %227[%310 : i64] : vector<4xi32>
          %312 = llvm.add %311, %309  : i32
          %313 = llvm.insertelement %312, %306[%3 : i64] : vector<16xi32>
          %314 = llvm.extractvalue %196[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %315 = llvm.mlir.constant(0 : i64) : i64
          %316 = llvm.extractelement %314[%315 : i64] : vector<4xi32>
          %317 = llvm.mlir.constant(0 : i64) : i64
          %318 = llvm.extractelement %242[%317 : i64] : vector<4xi32>
          %319 = llvm.add %318, %316  : i32
          %320 = llvm.insertelement %319, %313[%4 : i64] : vector<16xi32>
          %321 = llvm.extractvalue %196[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %322 = llvm.mlir.constant(1 : i64) : i64
          %323 = llvm.extractelement %321[%322 : i64] : vector<4xi32>
          %324 = llvm.mlir.constant(1 : i64) : i64
          %325 = llvm.extractelement %242[%324 : i64] : vector<4xi32>
          %326 = llvm.add %325, %323  : i32
          %327 = llvm.insertelement %326, %320[%5 : i64] : vector<16xi32>
          %328 = llvm.extractvalue %196[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %329 = llvm.mlir.constant(2 : i64) : i64
          %330 = llvm.extractelement %328[%329 : i64] : vector<4xi32>
          %331 = llvm.mlir.constant(2 : i64) : i64
          %332 = llvm.extractelement %242[%331 : i64] : vector<4xi32>
          %333 = llvm.add %332, %330  : i32
          %334 = llvm.insertelement %333, %327[%6 : i64] : vector<16xi32>
          %335 = llvm.extractvalue %196[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %336 = llvm.mlir.constant(3 : i64) : i64
          %337 = llvm.extractelement %335[%336 : i64] : vector<4xi32>
          %338 = llvm.mlir.constant(3 : i64) : i64
          %339 = llvm.extractelement %242[%338 : i64] : vector<4xi32>
          %340 = llvm.add %339, %337  : i32
          %341 = llvm.insertelement %340, %334[%7 : i64] : vector<16xi32>
          %342 = llvm.extractvalue %196[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %343 = llvm.mlir.constant(0 : i64) : i64
          %344 = llvm.extractelement %342[%343 : i64] : vector<4xi32>
          %345 = llvm.mlir.constant(0 : i64) : i64
          %346 = llvm.extractelement %257[%345 : i64] : vector<4xi32>
          %347 = llvm.add %346, %344  : i32
          %348 = llvm.insertelement %347, %341[%8 : i64] : vector<16xi32>
          %349 = llvm.extractvalue %196[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %350 = llvm.mlir.constant(1 : i64) : i64
          %351 = llvm.extractelement %349[%350 : i64] : vector<4xi32>
          %352 = llvm.mlir.constant(1 : i64) : i64
          %353 = llvm.extractelement %257[%352 : i64] : vector<4xi32>
          %354 = llvm.add %353, %351  : i32
          %355 = llvm.insertelement %354, %348[%9 : i64] : vector<16xi32>
          %356 = llvm.extractvalue %196[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %357 = llvm.mlir.constant(2 : i64) : i64
          %358 = llvm.extractelement %356[%357 : i64] : vector<4xi32>
          %359 = llvm.mlir.constant(2 : i64) : i64
          %360 = llvm.extractelement %257[%359 : i64] : vector<4xi32>
          %361 = llvm.add %360, %358  : i32
          %362 = llvm.insertelement %361, %355[%10 : i64] : vector<16xi32>
          %363 = llvm.extractvalue %196[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %364 = llvm.mlir.constant(3 : i64) : i64
          %365 = llvm.extractelement %363[%364 : i64] : vector<4xi32>
          %366 = llvm.mlir.constant(3 : i64) : i64
          %367 = llvm.extractelement %257[%366 : i64] : vector<4xi32>
          %368 = llvm.add %367, %365  : i32
          %369 = llvm.insertelement %368, %362[%11 : i64] : vector<16xi32>
          %370 = llvm.mlir.constant(0 : i64) : i64
          %371 = llvm.extractelement %369[%370 : i64] : vector<16xi32>
          %372 = llvm.extractvalue %15[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %373 = llvm.mlir.constant(0 : i64) : i64
          %374 = llvm.insertelement %371, %372[%373 : i64] : vector<4xi32>
          %375 = llvm.insertvalue %374, %15[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %376 = llvm.mlir.constant(1 : i64) : i64
          %377 = llvm.extractelement %369[%376 : i64] : vector<16xi32>
          %378 = llvm.extractvalue %375[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %379 = llvm.mlir.constant(1 : i64) : i64
          %380 = llvm.insertelement %377, %378[%379 : i64] : vector<4xi32>
          %381 = llvm.insertvalue %380, %375[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %382 = llvm.mlir.constant(2 : i64) : i64
          %383 = llvm.extractelement %369[%382 : i64] : vector<16xi32>
          %384 = llvm.extractvalue %381[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %385 = llvm.mlir.constant(2 : i64) : i64
          %386 = llvm.insertelement %383, %384[%385 : i64] : vector<4xi32>
          %387 = llvm.insertvalue %386, %381[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %388 = llvm.mlir.constant(3 : i64) : i64
          %389 = llvm.extractelement %369[%388 : i64] : vector<16xi32>
          %390 = llvm.extractvalue %387[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %391 = llvm.mlir.constant(3 : i64) : i64
          %392 = llvm.insertelement %389, %390[%391 : i64] : vector<4xi32>
          %393 = llvm.insertvalue %392, %387[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %394 = llvm.mlir.constant(4 : i64) : i64
          %395 = llvm.extractelement %369[%394 : i64] : vector<16xi32>
          %396 = llvm.extractvalue %393[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %397 = llvm.mlir.constant(0 : i64) : i64
          %398 = llvm.insertelement %395, %396[%397 : i64] : vector<4xi32>
          %399 = llvm.insertvalue %398, %393[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %400 = llvm.mlir.constant(5 : i64) : i64
          %401 = llvm.extractelement %369[%400 : i64] : vector<16xi32>
          %402 = llvm.extractvalue %399[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %403 = llvm.mlir.constant(1 : i64) : i64
          %404 = llvm.insertelement %401, %402[%403 : i64] : vector<4xi32>
          %405 = llvm.insertvalue %404, %399[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %406 = llvm.mlir.constant(6 : i64) : i64
          %407 = llvm.extractelement %369[%406 : i64] : vector<16xi32>
          %408 = llvm.extractvalue %405[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %409 = llvm.mlir.constant(2 : i64) : i64
          %410 = llvm.insertelement %407, %408[%409 : i64] : vector<4xi32>
          %411 = llvm.insertvalue %410, %405[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %412 = llvm.mlir.constant(7 : i64) : i64
          %413 = llvm.extractelement %369[%412 : i64] : vector<16xi32>
          %414 = llvm.extractvalue %411[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %415 = llvm.mlir.constant(3 : i64) : i64
          %416 = llvm.insertelement %413, %414[%415 : i64] : vector<4xi32>
          %417 = llvm.insertvalue %416, %411[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %418 = llvm.mlir.constant(8 : i64) : i64
          %419 = llvm.extractelement %369[%418 : i64] : vector<16xi32>
          %420 = llvm.extractvalue %417[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %421 = llvm.mlir.constant(0 : i64) : i64
          %422 = llvm.insertelement %419, %420[%421 : i64] : vector<4xi32>
          %423 = llvm.insertvalue %422, %417[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %424 = llvm.mlir.constant(9 : i64) : i64
          %425 = llvm.extractelement %369[%424 : i64] : vector<16xi32>
          %426 = llvm.extractvalue %423[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %427 = llvm.mlir.constant(1 : i64) : i64
          %428 = llvm.insertelement %425, %426[%427 : i64] : vector<4xi32>
          %429 = llvm.insertvalue %428, %423[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %430 = llvm.mlir.constant(10 : i64) : i64
          %431 = llvm.extractelement %369[%430 : i64] : vector<16xi32>
          %432 = llvm.extractvalue %429[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %433 = llvm.mlir.constant(2 : i64) : i64
          %434 = llvm.insertelement %431, %432[%433 : i64] : vector<4xi32>
          %435 = llvm.insertvalue %434, %429[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %436 = llvm.mlir.constant(11 : i64) : i64
          %437 = llvm.extractelement %369[%436 : i64] : vector<16xi32>
          %438 = llvm.extractvalue %435[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %439 = llvm.mlir.constant(3 : i64) : i64
          %440 = llvm.insertelement %437, %438[%439 : i64] : vector<4xi32>
          %441 = llvm.insertvalue %440, %435[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %442 = llvm.mlir.constant(12 : i64) : i64
          %443 = llvm.extractelement %369[%442 : i64] : vector<16xi32>
          %444 = llvm.extractvalue %441[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %445 = llvm.mlir.constant(0 : i64) : i64
          %446 = llvm.insertelement %443, %444[%445 : i64] : vector<4xi32>
          %447 = llvm.insertvalue %446, %441[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %448 = llvm.mlir.constant(13 : i64) : i64
          %449 = llvm.extractelement %369[%448 : i64] : vector<16xi32>
          %450 = llvm.extractvalue %447[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %451 = llvm.mlir.constant(1 : i64) : i64
          %452 = llvm.insertelement %449, %450[%451 : i64] : vector<4xi32>
          %453 = llvm.insertvalue %452, %447[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %454 = llvm.mlir.constant(14 : i64) : i64
          %455 = llvm.extractelement %369[%454 : i64] : vector<16xi32>
          %456 = llvm.extractvalue %453[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %457 = llvm.mlir.constant(2 : i64) : i64
          %458 = llvm.insertelement %455, %456[%457 : i64] : vector<4xi32>
          %459 = llvm.insertvalue %458, %453[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %460 = llvm.mlir.constant(15 : i64) : i64
          %461 = llvm.extractelement %369[%460 : i64] : vector<16xi32>
          %462 = llvm.extractvalue %459[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %463 = llvm.mlir.constant(3 : i64) : i64
          %464 = llvm.insertelement %461, %462[%463 : i64] : vector<4xi32>
          %465 = llvm.insertvalue %464, %459[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %466 = llvm.add %195, %17  : i64
          llvm.br ^bb4(%466, %465 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %467 = llvm.extractvalue %105[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %468 = llvm.extractvalue %105[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %469 = llvm.mlir.constant(256 : index) : i64
          %470 = llvm.mul %137, %469  : i64
          %471 = llvm.add %468, %470  : i64
          %472 = llvm.add %471, %139  : i64
          %473 = llvm.getelementptr %467[%472] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %474 = llvm.bitcast %473 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %475 = llvm.load %474 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %476 = llvm.extractvalue %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %477 = llvm.mlir.constant(0 : i64) : i64
          %478 = llvm.extractelement %475[%477 : i64] : vector<4xi32>
          %479 = "llvm.intr.vector.reduce.add"(%476) : (vector<4xi32>) -> i32
          %480 = llvm.add %478, %479  : i32
          %481 = llvm.insertelement %480, %12[%19 : i64] : vector<4xi32>
          %482 = llvm.extractvalue %196[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %483 = llvm.mlir.constant(1 : i64) : i64
          %484 = llvm.extractelement %475[%483 : i64] : vector<4xi32>
          %485 = "llvm.intr.vector.reduce.add"(%482) : (vector<4xi32>) -> i32
          %486 = llvm.add %484, %485  : i32
          %487 = llvm.insertelement %486, %481[%17 : i64] : vector<4xi32>
          %488 = llvm.extractvalue %196[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %489 = llvm.mlir.constant(2 : i64) : i64
          %490 = llvm.extractelement %475[%489 : i64] : vector<4xi32>
          %491 = "llvm.intr.vector.reduce.add"(%488) : (vector<4xi32>) -> i32
          %492 = llvm.add %490, %491  : i32
          %493 = llvm.insertelement %492, %487[%13 : i64] : vector<4xi32>
          %494 = llvm.extractvalue %196[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %495 = llvm.mlir.constant(3 : i64) : i64
          %496 = llvm.extractelement %475[%495 : i64] : vector<4xi32>
          %497 = "llvm.intr.vector.reduce.add"(%494) : (vector<4xi32>) -> i32
          %498 = llvm.add %496, %497  : i32
          %499 = llvm.insertelement %498, %493[%14 : i64] : vector<4xi32>
          %500 = llvm.extractvalue %105[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %501 = llvm.extractvalue %105[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %502 = llvm.mlir.constant(256 : index) : i64
          %503 = llvm.mul %137, %502  : i64
          %504 = llvm.add %501, %503  : i64
          %505 = llvm.add %504, %139  : i64
          %506 = llvm.getelementptr %500[%505] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %507 = llvm.bitcast %506 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          llvm.store %499, %507 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %508 = llvm.add %139, %16  : i64
          llvm.br ^bb2(%508 : i64)
        ^bb7:  // pred: ^bb2
          %509 = llvm.add %137, %17  : i64
          llvm.br ^bb1(%509 : i64)
        ^bb8:  // pred: ^bb1
          %510 = llvm.mlir.constant(0 : i32) : i32
          llvm.return %510 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After ReconcileUnrealizedCasts (reconcile-unrealized-casts) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 {
          %0 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %1 = llvm.mlir.constant(5 : index) : i64
          %2 = llvm.mlir.constant(6 : index) : i64
          %3 = llvm.mlir.constant(7 : index) : i64
          %4 = llvm.mlir.constant(8 : index) : i64
          %5 = llvm.mlir.constant(9 : index) : i64
          %6 = llvm.mlir.constant(10 : index) : i64
          %7 = llvm.mlir.constant(11 : index) : i64
          %8 = llvm.mlir.constant(12 : index) : i64
          %9 = llvm.mlir.constant(13 : index) : i64
          %10 = llvm.mlir.constant(14 : index) : i64
          %11 = llvm.mlir.constant(15 : index) : i64
          %12 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %13 = llvm.mlir.constant(2 : index) : i64
          %14 = llvm.mlir.constant(3 : index) : i64
          %15 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %16 = llvm.mlir.constant(4 : index) : i64
          %17 = llvm.mlir.constant(1 : index) : i64
          %18 = llvm.mlir.constant(32 : index) : i64
          %19 = llvm.mlir.constant(0 : index) : i64
          %20 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %21 = llvm.extractvalue %20[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.load %21 : !llvm.ptr<ptr<i8>>
          %24 = llvm.bitcast %23 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %25 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)>
          %26 = llvm.insertvalue %24, %25[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %27 = llvm.insertvalue %24, %26[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %28 = llvm.mlir.constant(0 : index) : i64
          %29 = llvm.insertvalue %28, %27[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %30 = llvm.mlir.constant(512 : index) : i64
          %31 = llvm.insertvalue %30, %29[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %32 = llvm.mlir.constant(32768 : index) : i64
          %33 = llvm.insertvalue %32, %31[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %34 = llvm.mlir.constant(256 : index) : i64
          %35 = llvm.insertvalue %34, %33[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %36 = llvm.mlir.constant(128 : index) : i64
          %37 = llvm.insertvalue %36, %35[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %38 = llvm.mlir.constant(128 : index) : i64
          %39 = llvm.insertvalue %38, %37[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.insertvalue %40, %39[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.mlir.constant(63 : index) : i64
          %44 = llvm.ptrtoint %24 : !llvm.ptr<i32> to i64
          %45 = llvm.and %44, %43  : i64
          %46 = llvm.icmp "eq" %45, %42 : i64
          "llvm.intr.assume"(%46) : (i1) -> ()
          %47 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %48 = llvm.extractvalue %47[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %49 = llvm.mlir.constant(1 : i64) : i64
          %50 = llvm.getelementptr %48[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %51 = llvm.load %50 : !llvm.ptr<ptr<i8>>
          %52 = llvm.bitcast %51 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %53 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)>
          %54 = llvm.insertvalue %52, %53[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %55 = llvm.insertvalue %52, %54[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %56 = llvm.mlir.constant(0 : index) : i64
          %57 = llvm.insertvalue %56, %55[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %58 = llvm.mlir.constant(512 : index) : i64
          %59 = llvm.insertvalue %58, %57[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %60 = llvm.mlir.constant(256 : index) : i64
          %61 = llvm.insertvalue %60, %59[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %62 = llvm.mlir.constant(256 : index) : i64
          %63 = llvm.insertvalue %62, %61[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %64 = llvm.mlir.constant(1 : index) : i64
          %65 = llvm.insertvalue %64, %63[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %66 = llvm.mlir.constant(0 : index) : i64
          %67 = llvm.mlir.constant(63 : index) : i64
          %68 = llvm.ptrtoint %52 : !llvm.ptr<i32> to i64
          %69 = llvm.and %68, %67  : i64
          %70 = llvm.icmp "eq" %69, %66 : i64
          "llvm.intr.assume"(%70) : (i1) -> ()
          %71 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %72 = llvm.extractvalue %71[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %73 = llvm.zext %72 : i32 to i64
          %74 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %75 = llvm.extractvalue %74[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %76 = llvm.zext %75 : i32 to i64
          %77 = llvm.mlir.constant(32 : index) : i64
          %78 = llvm.mul %76, %77  : i64
          %79 = llvm.mlir.constant(32 : index) : i64
          %80 = llvm.mul %73, %79  : i64
          %81 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)>
          %82 = llvm.insertvalue %52, %81[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %83 = llvm.insertvalue %52, %82[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %84 = llvm.mul %78, %60  : i64
          %85 = llvm.add %56, %84  : i64
          %86 = llvm.mul %80, %64  : i64
          %87 = llvm.add %85, %86  : i64
          %88 = llvm.insertvalue %87, %83[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %89 = llvm.mlir.constant(32 : i64) : i64
          %90 = llvm.mlir.constant(1 : i64) : i64
          %91 = llvm.insertvalue %89, %88[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %92 = llvm.insertvalue %90, %91[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %93 = llvm.mlir.constant(32 : i64) : i64
          %94 = llvm.mlir.constant(256 : i64) : i64
          %95 = llvm.insertvalue %93, %92[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %96 = llvm.insertvalue %94, %95[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %97 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)>
          %98 = llvm.insertvalue %24, %97[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %99 = llvm.insertvalue %24, %98[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %100 = llvm.mul %78, %32  : i64
          %101 = llvm.add %28, %100  : i64
          %102 = llvm.mul %80, %36  : i64
          %103 = llvm.add %101, %102  : i64
          %104 = llvm.mlir.constant(0 : i64) : i64
          %105 = llvm.mul %104, %40  : i64
          %106 = llvm.add %103, %105  : i64
          %107 = llvm.insertvalue %106, %99[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %108 = llvm.mlir.constant(128 : i64) : i64
          %109 = llvm.mlir.constant(1 : i64) : i64
          %110 = llvm.insertvalue %108, %107[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %111 = llvm.insertvalue %109, %110[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %112 = llvm.mlir.constant(32 : i64) : i64
          %113 = llvm.mlir.constant(128 : i64) : i64
          %114 = llvm.insertvalue %112, %111[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %115 = llvm.insertvalue %113, %114[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %116 = llvm.mlir.constant(32 : i64) : i64
          %117 = llvm.mlir.constant(32768 : i64) : i64
          %118 = llvm.insertvalue %116, %115[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %119 = llvm.insertvalue %117, %118[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          llvm.br ^bb1(%19 : i64)
        ^bb1(%120: i64):  // 2 preds: ^bb0, ^bb7
          %121 = llvm.icmp "slt" %120, %18 : i64
          llvm.cond_br %121, ^bb2(%19 : i64), ^bb8
        ^bb2(%122: i64):  // 2 preds: ^bb1, ^bb6
          %123 = llvm.icmp "slt" %122, %18 : i64
          llvm.cond_br %123, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %124 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)>
          %125 = llvm.insertvalue %24, %124[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %126 = llvm.insertvalue %24, %125[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %127 = llvm.mul %120, %117  : i64
          %128 = llvm.add %106, %127  : i64
          %129 = llvm.mul %122, %113  : i64
          %130 = llvm.add %128, %129  : i64
          %131 = llvm.mlir.constant(0 : i64) : i64
          %132 = llvm.mul %131, %109  : i64
          %133 = llvm.add %130, %132  : i64
          %134 = llvm.insertvalue %133, %126[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %135 = llvm.mlir.constant(128 : i64) : i64
          %136 = llvm.mlir.constant(1 : i64) : i64
          %137 = llvm.insertvalue %135, %134[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %138 = llvm.insertvalue %136, %137[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %139 = llvm.mlir.constant(4 : i64) : i64
          %140 = llvm.mlir.constant(128 : i64) : i64
          %141 = llvm.insertvalue %139, %138[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %142 = llvm.insertvalue %140, %141[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %143 = llvm.mlir.constant(1 : i64) : i64
          %144 = llvm.mlir.constant(32768 : i64) : i64
          %145 = llvm.insertvalue %143, %142[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %146 = llvm.insertvalue %144, %145[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %147 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)>
          %148 = llvm.insertvalue %24, %147[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %149 = llvm.insertvalue %24, %148[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %150 = llvm.insertvalue %133, %149[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %151 = llvm.mlir.constant(1 : index) : i64
          %152 = llvm.mlir.constant(4 : index) : i64
          %153 = llvm.mlir.constant(32 : index) : i64
          %154 = llvm.mlir.constant(4 : index) : i64
          %155 = llvm.insertvalue %151, %150[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %156 = llvm.insertvalue %152, %155[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %157 = llvm.insertvalue %153, %156[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %158 = llvm.insertvalue %154, %157[3, 3] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %159 = llvm.mlir.constant(32768 : index) : i64
          %160 = llvm.insertvalue %159, %158[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %161 = llvm.mlir.constant(128 : index) : i64
          %162 = llvm.insertvalue %161, %160[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %163 = llvm.mlir.constant(4 : index) : i64
          %164 = llvm.insertvalue %163, %162[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %165 = llvm.mlir.constant(1 : index) : i64
          %166 = llvm.insertvalue %165, %164[4, 3] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          llvm.br ^bb4(%19, %15 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%167: i64, %168: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %169 = llvm.icmp "slt" %167, %18 : i64
          llvm.cond_br %169, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %170 = llvm.mlir.constant(32768 : index) : i64
          %171 = llvm.mul %19, %170  : i64
          %172 = llvm.add %133, %171  : i64
          %173 = llvm.mlir.constant(128 : index) : i64
          %174 = llvm.mul %19, %173  : i64
          %175 = llvm.add %172, %174  : i64
          %176 = llvm.mlir.constant(4 : index) : i64
          %177 = llvm.mul %167, %176  : i64
          %178 = llvm.add %175, %177  : i64
          %179 = llvm.add %178, %19  : i64
          %180 = llvm.getelementptr %24[%179] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %181 = llvm.bitcast %180 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %182 = llvm.load %181 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %183 = llvm.mlir.constant(32768 : index) : i64
          %184 = llvm.mul %19, %183  : i64
          %185 = llvm.add %133, %184  : i64
          %186 = llvm.mlir.constant(128 : index) : i64
          %187 = llvm.mul %17, %186  : i64
          %188 = llvm.add %185, %187  : i64
          %189 = llvm.mlir.constant(4 : index) : i64
          %190 = llvm.mul %167, %189  : i64
          %191 = llvm.add %188, %190  : i64
          %192 = llvm.add %191, %19  : i64
          %193 = llvm.getelementptr %24[%192] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %194 = llvm.bitcast %193 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %195 = llvm.load %194 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %196 = llvm.mlir.constant(32768 : index) : i64
          %197 = llvm.mul %19, %196  : i64
          %198 = llvm.add %133, %197  : i64
          %199 = llvm.mlir.constant(128 : index) : i64
          %200 = llvm.mul %13, %199  : i64
          %201 = llvm.add %198, %200  : i64
          %202 = llvm.mlir.constant(4 : index) : i64
          %203 = llvm.mul %167, %202  : i64
          %204 = llvm.add %201, %203  : i64
          %205 = llvm.add %204, %19  : i64
          %206 = llvm.getelementptr %24[%205] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %207 = llvm.bitcast %206 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %208 = llvm.load %207 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %209 = llvm.mlir.constant(32768 : index) : i64
          %210 = llvm.mul %19, %209  : i64
          %211 = llvm.add %133, %210  : i64
          %212 = llvm.mlir.constant(128 : index) : i64
          %213 = llvm.mul %14, %212  : i64
          %214 = llvm.add %211, %213  : i64
          %215 = llvm.mlir.constant(4 : index) : i64
          %216 = llvm.mul %167, %215  : i64
          %217 = llvm.add %214, %216  : i64
          %218 = llvm.add %217, %19  : i64
          %219 = llvm.getelementptr %24[%218] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %220 = llvm.bitcast %219 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %221 = llvm.load %220 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %222 = llvm.extractvalue %168[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.mlir.constant(0 : i64) : i64
          %224 = llvm.extractelement %222[%223 : i64] : vector<4xi32>
          %225 = llvm.mlir.constant(0 : i64) : i64
          %226 = llvm.extractelement %182[%225 : i64] : vector<4xi32>
          %227 = llvm.add %226, %224  : i32
          %228 = llvm.insertelement %227, %0[%19 : i64] : vector<16xi32>
          %229 = llvm.extractvalue %168[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.mlir.constant(1 : i64) : i64
          %231 = llvm.extractelement %229[%230 : i64] : vector<4xi32>
          %232 = llvm.mlir.constant(1 : i64) : i64
          %233 = llvm.extractelement %182[%232 : i64] : vector<4xi32>
          %234 = llvm.add %233, %231  : i32
          %235 = llvm.insertelement %234, %228[%17 : i64] : vector<16xi32>
          %236 = llvm.extractvalue %168[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %237 = llvm.mlir.constant(2 : i64) : i64
          %238 = llvm.extractelement %236[%237 : i64] : vector<4xi32>
          %239 = llvm.mlir.constant(2 : i64) : i64
          %240 = llvm.extractelement %182[%239 : i64] : vector<4xi32>
          %241 = llvm.add %240, %238  : i32
          %242 = llvm.insertelement %241, %235[%13 : i64] : vector<16xi32>
          %243 = llvm.extractvalue %168[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %244 = llvm.mlir.constant(3 : i64) : i64
          %245 = llvm.extractelement %243[%244 : i64] : vector<4xi32>
          %246 = llvm.mlir.constant(3 : i64) : i64
          %247 = llvm.extractelement %182[%246 : i64] : vector<4xi32>
          %248 = llvm.add %247, %245  : i32
          %249 = llvm.insertelement %248, %242[%14 : i64] : vector<16xi32>
          %250 = llvm.extractvalue %168[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %251 = llvm.mlir.constant(0 : i64) : i64
          %252 = llvm.extractelement %250[%251 : i64] : vector<4xi32>
          %253 = llvm.mlir.constant(0 : i64) : i64
          %254 = llvm.extractelement %195[%253 : i64] : vector<4xi32>
          %255 = llvm.add %254, %252  : i32
          %256 = llvm.insertelement %255, %249[%16 : i64] : vector<16xi32>
          %257 = llvm.extractvalue %168[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %258 = llvm.mlir.constant(1 : i64) : i64
          %259 = llvm.extractelement %257[%258 : i64] : vector<4xi32>
          %260 = llvm.mlir.constant(1 : i64) : i64
          %261 = llvm.extractelement %195[%260 : i64] : vector<4xi32>
          %262 = llvm.add %261, %259  : i32
          %263 = llvm.insertelement %262, %256[%1 : i64] : vector<16xi32>
          %264 = llvm.extractvalue %168[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %265 = llvm.mlir.constant(2 : i64) : i64
          %266 = llvm.extractelement %264[%265 : i64] : vector<4xi32>
          %267 = llvm.mlir.constant(2 : i64) : i64
          %268 = llvm.extractelement %195[%267 : i64] : vector<4xi32>
          %269 = llvm.add %268, %266  : i32
          %270 = llvm.insertelement %269, %263[%2 : i64] : vector<16xi32>
          %271 = llvm.extractvalue %168[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %272 = llvm.mlir.constant(3 : i64) : i64
          %273 = llvm.extractelement %271[%272 : i64] : vector<4xi32>
          %274 = llvm.mlir.constant(3 : i64) : i64
          %275 = llvm.extractelement %195[%274 : i64] : vector<4xi32>
          %276 = llvm.add %275, %273  : i32
          %277 = llvm.insertelement %276, %270[%3 : i64] : vector<16xi32>
          %278 = llvm.extractvalue %168[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %279 = llvm.mlir.constant(0 : i64) : i64
          %280 = llvm.extractelement %278[%279 : i64] : vector<4xi32>
          %281 = llvm.mlir.constant(0 : i64) : i64
          %282 = llvm.extractelement %208[%281 : i64] : vector<4xi32>
          %283 = llvm.add %282, %280  : i32
          %284 = llvm.insertelement %283, %277[%4 : i64] : vector<16xi32>
          %285 = llvm.extractvalue %168[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %286 = llvm.mlir.constant(1 : i64) : i64
          %287 = llvm.extractelement %285[%286 : i64] : vector<4xi32>
          %288 = llvm.mlir.constant(1 : i64) : i64
          %289 = llvm.extractelement %208[%288 : i64] : vector<4xi32>
          %290 = llvm.add %289, %287  : i32
          %291 = llvm.insertelement %290, %284[%5 : i64] : vector<16xi32>
          %292 = llvm.extractvalue %168[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %293 = llvm.mlir.constant(2 : i64) : i64
          %294 = llvm.extractelement %292[%293 : i64] : vector<4xi32>
          %295 = llvm.mlir.constant(2 : i64) : i64
          %296 = llvm.extractelement %208[%295 : i64] : vector<4xi32>
          %297 = llvm.add %296, %294  : i32
          %298 = llvm.insertelement %297, %291[%6 : i64] : vector<16xi32>
          %299 = llvm.extractvalue %168[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %300 = llvm.mlir.constant(3 : i64) : i64
          %301 = llvm.extractelement %299[%300 : i64] : vector<4xi32>
          %302 = llvm.mlir.constant(3 : i64) : i64
          %303 = llvm.extractelement %208[%302 : i64] : vector<4xi32>
          %304 = llvm.add %303, %301  : i32
          %305 = llvm.insertelement %304, %298[%7 : i64] : vector<16xi32>
          %306 = llvm.extractvalue %168[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %307 = llvm.mlir.constant(0 : i64) : i64
          %308 = llvm.extractelement %306[%307 : i64] : vector<4xi32>
          %309 = llvm.mlir.constant(0 : i64) : i64
          %310 = llvm.extractelement %221[%309 : i64] : vector<4xi32>
          %311 = llvm.add %310, %308  : i32
          %312 = llvm.insertelement %311, %305[%8 : i64] : vector<16xi32>
          %313 = llvm.extractvalue %168[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %314 = llvm.mlir.constant(1 : i64) : i64
          %315 = llvm.extractelement %313[%314 : i64] : vector<4xi32>
          %316 = llvm.mlir.constant(1 : i64) : i64
          %317 = llvm.extractelement %221[%316 : i64] : vector<4xi32>
          %318 = llvm.add %317, %315  : i32
          %319 = llvm.insertelement %318, %312[%9 : i64] : vector<16xi32>
          %320 = llvm.extractvalue %168[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %321 = llvm.mlir.constant(2 : i64) : i64
          %322 = llvm.extractelement %320[%321 : i64] : vector<4xi32>
          %323 = llvm.mlir.constant(2 : i64) : i64
          %324 = llvm.extractelement %221[%323 : i64] : vector<4xi32>
          %325 = llvm.add %324, %322  : i32
          %326 = llvm.insertelement %325, %319[%10 : i64] : vector<16xi32>
          %327 = llvm.extractvalue %168[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %328 = llvm.mlir.constant(3 : i64) : i64
          %329 = llvm.extractelement %327[%328 : i64] : vector<4xi32>
          %330 = llvm.mlir.constant(3 : i64) : i64
          %331 = llvm.extractelement %221[%330 : i64] : vector<4xi32>
          %332 = llvm.add %331, %329  : i32
          %333 = llvm.insertelement %332, %326[%11 : i64] : vector<16xi32>
          %334 = llvm.mlir.constant(0 : i64) : i64
          %335 = llvm.extractelement %333[%334 : i64] : vector<16xi32>
          %336 = llvm.extractvalue %15[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %337 = llvm.mlir.constant(0 : i64) : i64
          %338 = llvm.insertelement %335, %336[%337 : i64] : vector<4xi32>
          %339 = llvm.insertvalue %338, %15[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %340 = llvm.mlir.constant(1 : i64) : i64
          %341 = llvm.extractelement %333[%340 : i64] : vector<16xi32>
          %342 = llvm.mlir.constant(1 : i64) : i64
          %343 = llvm.insertelement %341, %338[%342 : i64] : vector<4xi32>
          %344 = llvm.insertvalue %343, %339[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %345 = llvm.mlir.constant(2 : i64) : i64
          %346 = llvm.extractelement %333[%345 : i64] : vector<16xi32>
          %347 = llvm.mlir.constant(2 : i64) : i64
          %348 = llvm.insertelement %346, %343[%347 : i64] : vector<4xi32>
          %349 = llvm.insertvalue %348, %344[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %350 = llvm.mlir.constant(3 : i64) : i64
          %351 = llvm.extractelement %333[%350 : i64] : vector<16xi32>
          %352 = llvm.mlir.constant(3 : i64) : i64
          %353 = llvm.insertelement %351, %348[%352 : i64] : vector<4xi32>
          %354 = llvm.insertvalue %353, %349[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %355 = llvm.mlir.constant(4 : i64) : i64
          %356 = llvm.extractelement %333[%355 : i64] : vector<16xi32>
          %357 = llvm.extractvalue %15[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %358 = llvm.mlir.constant(0 : i64) : i64
          %359 = llvm.insertelement %356, %357[%358 : i64] : vector<4xi32>
          %360 = llvm.insertvalue %359, %354[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %361 = llvm.mlir.constant(5 : i64) : i64
          %362 = llvm.extractelement %333[%361 : i64] : vector<16xi32>
          %363 = llvm.mlir.constant(1 : i64) : i64
          %364 = llvm.insertelement %362, %359[%363 : i64] : vector<4xi32>
          %365 = llvm.insertvalue %364, %360[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %366 = llvm.mlir.constant(6 : i64) : i64
          %367 = llvm.extractelement %333[%366 : i64] : vector<16xi32>
          %368 = llvm.mlir.constant(2 : i64) : i64
          %369 = llvm.insertelement %367, %364[%368 : i64] : vector<4xi32>
          %370 = llvm.insertvalue %369, %365[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %371 = llvm.mlir.constant(7 : i64) : i64
          %372 = llvm.extractelement %333[%371 : i64] : vector<16xi32>
          %373 = llvm.mlir.constant(3 : i64) : i64
          %374 = llvm.insertelement %372, %369[%373 : i64] : vector<4xi32>
          %375 = llvm.insertvalue %374, %370[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %376 = llvm.mlir.constant(8 : i64) : i64
          %377 = llvm.extractelement %333[%376 : i64] : vector<16xi32>
          %378 = llvm.extractvalue %15[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %379 = llvm.mlir.constant(0 : i64) : i64
          %380 = llvm.insertelement %377, %378[%379 : i64] : vector<4xi32>
          %381 = llvm.insertvalue %380, %375[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %382 = llvm.mlir.constant(9 : i64) : i64
          %383 = llvm.extractelement %333[%382 : i64] : vector<16xi32>
          %384 = llvm.mlir.constant(1 : i64) : i64
          %385 = llvm.insertelement %383, %380[%384 : i64] : vector<4xi32>
          %386 = llvm.insertvalue %385, %381[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %387 = llvm.mlir.constant(10 : i64) : i64
          %388 = llvm.extractelement %333[%387 : i64] : vector<16xi32>
          %389 = llvm.mlir.constant(2 : i64) : i64
          %390 = llvm.insertelement %388, %385[%389 : i64] : vector<4xi32>
          %391 = llvm.insertvalue %390, %386[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %392 = llvm.mlir.constant(11 : i64) : i64
          %393 = llvm.extractelement %333[%392 : i64] : vector<16xi32>
          %394 = llvm.mlir.constant(3 : i64) : i64
          %395 = llvm.insertelement %393, %390[%394 : i64] : vector<4xi32>
          %396 = llvm.insertvalue %395, %391[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %397 = llvm.mlir.constant(12 : i64) : i64
          %398 = llvm.extractelement %333[%397 : i64] : vector<16xi32>
          %399 = llvm.extractvalue %15[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %400 = llvm.mlir.constant(0 : i64) : i64
          %401 = llvm.insertelement %398, %399[%400 : i64] : vector<4xi32>
          %402 = llvm.insertvalue %401, %396[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %403 = llvm.mlir.constant(13 : i64) : i64
          %404 = llvm.extractelement %333[%403 : i64] : vector<16xi32>
          %405 = llvm.mlir.constant(1 : i64) : i64
          %406 = llvm.insertelement %404, %401[%405 : i64] : vector<4xi32>
          %407 = llvm.insertvalue %406, %402[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %408 = llvm.mlir.constant(14 : i64) : i64
          %409 = llvm.extractelement %333[%408 : i64] : vector<16xi32>
          %410 = llvm.mlir.constant(2 : i64) : i64
          %411 = llvm.insertelement %409, %406[%410 : i64] : vector<4xi32>
          %412 = llvm.insertvalue %411, %407[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %413 = llvm.mlir.constant(15 : i64) : i64
          %414 = llvm.extractelement %333[%413 : i64] : vector<16xi32>
          %415 = llvm.mlir.constant(3 : i64) : i64
          %416 = llvm.insertelement %414, %411[%415 : i64] : vector<4xi32>
          %417 = llvm.insertvalue %416, %412[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %418 = llvm.add %167, %17  : i64
          llvm.br ^bb4(%418, %417 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %419 = llvm.mlir.constant(256 : index) : i64
          %420 = llvm.mul %120, %419  : i64
          %421 = llvm.add %87, %420  : i64
          %422 = llvm.add %421, %122  : i64
          %423 = llvm.getelementptr %52[%422] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %424 = llvm.bitcast %423 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %425 = llvm.load %424 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %426 = llvm.extractvalue %168[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %427 = llvm.mlir.constant(0 : i64) : i64
          %428 = llvm.extractelement %425[%427 : i64] : vector<4xi32>
          %429 = "llvm.intr.vector.reduce.add"(%426) : (vector<4xi32>) -> i32
          %430 = llvm.add %428, %429  : i32
          %431 = llvm.insertelement %430, %12[%19 : i64] : vector<4xi32>
          %432 = llvm.extractvalue %168[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %433 = llvm.mlir.constant(1 : i64) : i64
          %434 = llvm.extractelement %425[%433 : i64] : vector<4xi32>
          %435 = "llvm.intr.vector.reduce.add"(%432) : (vector<4xi32>) -> i32
          %436 = llvm.add %434, %435  : i32
          %437 = llvm.insertelement %436, %431[%17 : i64] : vector<4xi32>
          %438 = llvm.extractvalue %168[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %439 = llvm.mlir.constant(2 : i64) : i64
          %440 = llvm.extractelement %425[%439 : i64] : vector<4xi32>
          %441 = "llvm.intr.vector.reduce.add"(%438) : (vector<4xi32>) -> i32
          %442 = llvm.add %440, %441  : i32
          %443 = llvm.insertelement %442, %437[%13 : i64] : vector<4xi32>
          %444 = llvm.extractvalue %168[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %445 = llvm.mlir.constant(3 : i64) : i64
          %446 = llvm.extractelement %425[%445 : i64] : vector<4xi32>
          %447 = "llvm.intr.vector.reduce.add"(%444) : (vector<4xi32>) -> i32
          %448 = llvm.add %446, %447  : i32
          %449 = llvm.insertelement %448, %443[%14 : i64] : vector<4xi32>
          %450 = llvm.mlir.constant(256 : index) : i64
          %451 = llvm.mul %120, %450  : i64
          %452 = llvm.add %87, %451  : i64
          %453 = llvm.add %452, %122  : i64
          %454 = llvm.getelementptr %52[%453] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %455 = llvm.bitcast %454 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          llvm.store %449, %455 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %456 = llvm.add %122, %16  : i64
          llvm.br ^bb2(%456 : i64)
        ^bb7:  // pred: ^bb2
          %457 = llvm.add %120, %17  : i64
          llvm.br ^bb1(%457 : i64)
        ^bb8:  // pred: ^bb1
          %458 = llvm.mlir.constant(0 : i32) : i32
          llvm.return %458 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After LLVMCPUSynchronizeSymbolVisibility (iree-llvmcpu-synchronize-symbol-visibility) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %1 = llvm.mlir.constant(5 : index) : i64
          %2 = llvm.mlir.constant(6 : index) : i64
          %3 = llvm.mlir.constant(7 : index) : i64
          %4 = llvm.mlir.constant(8 : index) : i64
          %5 = llvm.mlir.constant(9 : index) : i64
          %6 = llvm.mlir.constant(10 : index) : i64
          %7 = llvm.mlir.constant(11 : index) : i64
          %8 = llvm.mlir.constant(12 : index) : i64
          %9 = llvm.mlir.constant(13 : index) : i64
          %10 = llvm.mlir.constant(14 : index) : i64
          %11 = llvm.mlir.constant(15 : index) : i64
          %12 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %13 = llvm.mlir.constant(2 : index) : i64
          %14 = llvm.mlir.constant(3 : index) : i64
          %15 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %16 = llvm.mlir.constant(4 : index) : i64
          %17 = llvm.mlir.constant(1 : index) : i64
          %18 = llvm.mlir.constant(32 : index) : i64
          %19 = llvm.mlir.constant(0 : index) : i64
          %20 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %21 = llvm.extractvalue %20[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.load %21 : !llvm.ptr<ptr<i8>>
          %24 = llvm.bitcast %23 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %25 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)>
          %26 = llvm.insertvalue %24, %25[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %27 = llvm.insertvalue %24, %26[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %28 = llvm.mlir.constant(0 : index) : i64
          %29 = llvm.insertvalue %28, %27[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %30 = llvm.mlir.constant(512 : index) : i64
          %31 = llvm.insertvalue %30, %29[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %32 = llvm.mlir.constant(32768 : index) : i64
          %33 = llvm.insertvalue %32, %31[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %34 = llvm.mlir.constant(256 : index) : i64
          %35 = llvm.insertvalue %34, %33[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %36 = llvm.mlir.constant(128 : index) : i64
          %37 = llvm.insertvalue %36, %35[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %38 = llvm.mlir.constant(128 : index) : i64
          %39 = llvm.insertvalue %38, %37[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.insertvalue %40, %39[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.mlir.constant(63 : index) : i64
          %44 = llvm.ptrtoint %24 : !llvm.ptr<i32> to i64
          %45 = llvm.and %44, %43  : i64
          %46 = llvm.icmp "eq" %45, %42 : i64
          "llvm.intr.assume"(%46) : (i1) -> ()
          %47 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %48 = llvm.extractvalue %47[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %49 = llvm.mlir.constant(1 : i64) : i64
          %50 = llvm.getelementptr %48[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %51 = llvm.load %50 : !llvm.ptr<ptr<i8>>
          %52 = llvm.bitcast %51 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %53 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)>
          %54 = llvm.insertvalue %52, %53[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %55 = llvm.insertvalue %52, %54[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %56 = llvm.mlir.constant(0 : index) : i64
          %57 = llvm.insertvalue %56, %55[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %58 = llvm.mlir.constant(512 : index) : i64
          %59 = llvm.insertvalue %58, %57[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %60 = llvm.mlir.constant(256 : index) : i64
          %61 = llvm.insertvalue %60, %59[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %62 = llvm.mlir.constant(256 : index) : i64
          %63 = llvm.insertvalue %62, %61[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %64 = llvm.mlir.constant(1 : index) : i64
          %65 = llvm.insertvalue %64, %63[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %66 = llvm.mlir.constant(0 : index) : i64
          %67 = llvm.mlir.constant(63 : index) : i64
          %68 = llvm.ptrtoint %52 : !llvm.ptr<i32> to i64
          %69 = llvm.and %68, %67  : i64
          %70 = llvm.icmp "eq" %69, %66 : i64
          "llvm.intr.assume"(%70) : (i1) -> ()
          %71 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %72 = llvm.extractvalue %71[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %73 = llvm.zext %72 : i32 to i64
          %74 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %75 = llvm.extractvalue %74[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %76 = llvm.zext %75 : i32 to i64
          %77 = llvm.mlir.constant(32 : index) : i64
          %78 = llvm.mul %76, %77  : i64
          %79 = llvm.mlir.constant(32 : index) : i64
          %80 = llvm.mul %73, %79  : i64
          %81 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)>
          %82 = llvm.insertvalue %52, %81[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %83 = llvm.insertvalue %52, %82[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %84 = llvm.mul %78, %60  : i64
          %85 = llvm.add %56, %84  : i64
          %86 = llvm.mul %80, %64  : i64
          %87 = llvm.add %85, %86  : i64
          %88 = llvm.insertvalue %87, %83[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %89 = llvm.mlir.constant(32 : i64) : i64
          %90 = llvm.mlir.constant(1 : i64) : i64
          %91 = llvm.insertvalue %89, %88[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %92 = llvm.insertvalue %90, %91[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %93 = llvm.mlir.constant(32 : i64) : i64
          %94 = llvm.mlir.constant(256 : i64) : i64
          %95 = llvm.insertvalue %93, %92[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %96 = llvm.insertvalue %94, %95[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<2 x i64>, array<2 x i64>)> 
          %97 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)>
          %98 = llvm.insertvalue %24, %97[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %99 = llvm.insertvalue %24, %98[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %100 = llvm.mul %78, %32  : i64
          %101 = llvm.add %28, %100  : i64
          %102 = llvm.mul %80, %36  : i64
          %103 = llvm.add %101, %102  : i64
          %104 = llvm.mlir.constant(0 : i64) : i64
          %105 = llvm.mul %104, %40  : i64
          %106 = llvm.add %103, %105  : i64
          %107 = llvm.insertvalue %106, %99[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %108 = llvm.mlir.constant(128 : i64) : i64
          %109 = llvm.mlir.constant(1 : i64) : i64
          %110 = llvm.insertvalue %108, %107[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %111 = llvm.insertvalue %109, %110[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %112 = llvm.mlir.constant(32 : i64) : i64
          %113 = llvm.mlir.constant(128 : i64) : i64
          %114 = llvm.insertvalue %112, %111[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %115 = llvm.insertvalue %113, %114[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %116 = llvm.mlir.constant(32 : i64) : i64
          %117 = llvm.mlir.constant(32768 : i64) : i64
          %118 = llvm.insertvalue %116, %115[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %119 = llvm.insertvalue %117, %118[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          llvm.br ^bb1(%19 : i64)
        ^bb1(%120: i64):  // 2 preds: ^bb0, ^bb7
          %121 = llvm.icmp "slt" %120, %18 : i64
          llvm.cond_br %121, ^bb2(%19 : i64), ^bb8
        ^bb2(%122: i64):  // 2 preds: ^bb1, ^bb6
          %123 = llvm.icmp "slt" %122, %18 : i64
          llvm.cond_br %123, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %124 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)>
          %125 = llvm.insertvalue %24, %124[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %126 = llvm.insertvalue %24, %125[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %127 = llvm.mul %120, %117  : i64
          %128 = llvm.add %106, %127  : i64
          %129 = llvm.mul %122, %113  : i64
          %130 = llvm.add %128, %129  : i64
          %131 = llvm.mlir.constant(0 : i64) : i64
          %132 = llvm.mul %131, %109  : i64
          %133 = llvm.add %130, %132  : i64
          %134 = llvm.insertvalue %133, %126[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %135 = llvm.mlir.constant(128 : i64) : i64
          %136 = llvm.mlir.constant(1 : i64) : i64
          %137 = llvm.insertvalue %135, %134[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %138 = llvm.insertvalue %136, %137[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %139 = llvm.mlir.constant(4 : i64) : i64
          %140 = llvm.mlir.constant(128 : i64) : i64
          %141 = llvm.insertvalue %139, %138[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %142 = llvm.insertvalue %140, %141[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %143 = llvm.mlir.constant(1 : i64) : i64
          %144 = llvm.mlir.constant(32768 : i64) : i64
          %145 = llvm.insertvalue %143, %142[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %146 = llvm.insertvalue %144, %145[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<3 x i64>, array<3 x i64>)> 
          %147 = llvm.mlir.undef : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)>
          %148 = llvm.insertvalue %24, %147[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %149 = llvm.insertvalue %24, %148[1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %150 = llvm.insertvalue %133, %149[2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %151 = llvm.mlir.constant(1 : index) : i64
          %152 = llvm.mlir.constant(4 : index) : i64
          %153 = llvm.mlir.constant(32 : index) : i64
          %154 = llvm.mlir.constant(4 : index) : i64
          %155 = llvm.insertvalue %151, %150[3, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %156 = llvm.insertvalue %152, %155[3, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %157 = llvm.insertvalue %153, %156[3, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %158 = llvm.insertvalue %154, %157[3, 3] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %159 = llvm.mlir.constant(32768 : index) : i64
          %160 = llvm.insertvalue %159, %158[4, 0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %161 = llvm.mlir.constant(128 : index) : i64
          %162 = llvm.insertvalue %161, %160[4, 1] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %163 = llvm.mlir.constant(4 : index) : i64
          %164 = llvm.insertvalue %163, %162[4, 2] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          %165 = llvm.mlir.constant(1 : index) : i64
          %166 = llvm.insertvalue %165, %164[4, 3] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<4 x i64>, array<4 x i64>)> 
          llvm.br ^bb4(%19, %15 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%167: i64, %168: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %169 = llvm.icmp "slt" %167, %18 : i64
          llvm.cond_br %169, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %170 = llvm.mlir.constant(32768 : index) : i64
          %171 = llvm.mul %19, %170  : i64
          %172 = llvm.add %133, %171  : i64
          %173 = llvm.mlir.constant(128 : index) : i64
          %174 = llvm.mul %19, %173  : i64
          %175 = llvm.add %172, %174  : i64
          %176 = llvm.mlir.constant(4 : index) : i64
          %177 = llvm.mul %167, %176  : i64
          %178 = llvm.add %175, %177  : i64
          %179 = llvm.add %178, %19  : i64
          %180 = llvm.getelementptr %24[%179] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %181 = llvm.bitcast %180 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %182 = llvm.load %181 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %183 = llvm.mlir.constant(32768 : index) : i64
          %184 = llvm.mul %19, %183  : i64
          %185 = llvm.add %133, %184  : i64
          %186 = llvm.mlir.constant(128 : index) : i64
          %187 = llvm.mul %17, %186  : i64
          %188 = llvm.add %185, %187  : i64
          %189 = llvm.mlir.constant(4 : index) : i64
          %190 = llvm.mul %167, %189  : i64
          %191 = llvm.add %188, %190  : i64
          %192 = llvm.add %191, %19  : i64
          %193 = llvm.getelementptr %24[%192] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %194 = llvm.bitcast %193 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %195 = llvm.load %194 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %196 = llvm.mlir.constant(32768 : index) : i64
          %197 = llvm.mul %19, %196  : i64
          %198 = llvm.add %133, %197  : i64
          %199 = llvm.mlir.constant(128 : index) : i64
          %200 = llvm.mul %13, %199  : i64
          %201 = llvm.add %198, %200  : i64
          %202 = llvm.mlir.constant(4 : index) : i64
          %203 = llvm.mul %167, %202  : i64
          %204 = llvm.add %201, %203  : i64
          %205 = llvm.add %204, %19  : i64
          %206 = llvm.getelementptr %24[%205] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %207 = llvm.bitcast %206 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %208 = llvm.load %207 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %209 = llvm.mlir.constant(32768 : index) : i64
          %210 = llvm.mul %19, %209  : i64
          %211 = llvm.add %133, %210  : i64
          %212 = llvm.mlir.constant(128 : index) : i64
          %213 = llvm.mul %14, %212  : i64
          %214 = llvm.add %211, %213  : i64
          %215 = llvm.mlir.constant(4 : index) : i64
          %216 = llvm.mul %167, %215  : i64
          %217 = llvm.add %214, %216  : i64
          %218 = llvm.add %217, %19  : i64
          %219 = llvm.getelementptr %24[%218] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %220 = llvm.bitcast %219 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %221 = llvm.load %220 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %222 = llvm.extractvalue %168[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.mlir.constant(0 : i64) : i64
          %224 = llvm.extractelement %222[%223 : i64] : vector<4xi32>
          %225 = llvm.mlir.constant(0 : i64) : i64
          %226 = llvm.extractelement %182[%225 : i64] : vector<4xi32>
          %227 = llvm.add %226, %224  : i32
          %228 = llvm.insertelement %227, %0[%19 : i64] : vector<16xi32>
          %229 = llvm.extractvalue %168[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.mlir.constant(1 : i64) : i64
          %231 = llvm.extractelement %229[%230 : i64] : vector<4xi32>
          %232 = llvm.mlir.constant(1 : i64) : i64
          %233 = llvm.extractelement %182[%232 : i64] : vector<4xi32>
          %234 = llvm.add %233, %231  : i32
          %235 = llvm.insertelement %234, %228[%17 : i64] : vector<16xi32>
          %236 = llvm.extractvalue %168[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %237 = llvm.mlir.constant(2 : i64) : i64
          %238 = llvm.extractelement %236[%237 : i64] : vector<4xi32>
          %239 = llvm.mlir.constant(2 : i64) : i64
          %240 = llvm.extractelement %182[%239 : i64] : vector<4xi32>
          %241 = llvm.add %240, %238  : i32
          %242 = llvm.insertelement %241, %235[%13 : i64] : vector<16xi32>
          %243 = llvm.extractvalue %168[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %244 = llvm.mlir.constant(3 : i64) : i64
          %245 = llvm.extractelement %243[%244 : i64] : vector<4xi32>
          %246 = llvm.mlir.constant(3 : i64) : i64
          %247 = llvm.extractelement %182[%246 : i64] : vector<4xi32>
          %248 = llvm.add %247, %245  : i32
          %249 = llvm.insertelement %248, %242[%14 : i64] : vector<16xi32>
          %250 = llvm.extractvalue %168[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %251 = llvm.mlir.constant(0 : i64) : i64
          %252 = llvm.extractelement %250[%251 : i64] : vector<4xi32>
          %253 = llvm.mlir.constant(0 : i64) : i64
          %254 = llvm.extractelement %195[%253 : i64] : vector<4xi32>
          %255 = llvm.add %254, %252  : i32
          %256 = llvm.insertelement %255, %249[%16 : i64] : vector<16xi32>
          %257 = llvm.extractvalue %168[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %258 = llvm.mlir.constant(1 : i64) : i64
          %259 = llvm.extractelement %257[%258 : i64] : vector<4xi32>
          %260 = llvm.mlir.constant(1 : i64) : i64
          %261 = llvm.extractelement %195[%260 : i64] : vector<4xi32>
          %262 = llvm.add %261, %259  : i32
          %263 = llvm.insertelement %262, %256[%1 : i64] : vector<16xi32>
          %264 = llvm.extractvalue %168[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %265 = llvm.mlir.constant(2 : i64) : i64
          %266 = llvm.extractelement %264[%265 : i64] : vector<4xi32>
          %267 = llvm.mlir.constant(2 : i64) : i64
          %268 = llvm.extractelement %195[%267 : i64] : vector<4xi32>
          %269 = llvm.add %268, %266  : i32
          %270 = llvm.insertelement %269, %263[%2 : i64] : vector<16xi32>
          %271 = llvm.extractvalue %168[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %272 = llvm.mlir.constant(3 : i64) : i64
          %273 = llvm.extractelement %271[%272 : i64] : vector<4xi32>
          %274 = llvm.mlir.constant(3 : i64) : i64
          %275 = llvm.extractelement %195[%274 : i64] : vector<4xi32>
          %276 = llvm.add %275, %273  : i32
          %277 = llvm.insertelement %276, %270[%3 : i64] : vector<16xi32>
          %278 = llvm.extractvalue %168[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %279 = llvm.mlir.constant(0 : i64) : i64
          %280 = llvm.extractelement %278[%279 : i64] : vector<4xi32>
          %281 = llvm.mlir.constant(0 : i64) : i64
          %282 = llvm.extractelement %208[%281 : i64] : vector<4xi32>
          %283 = llvm.add %282, %280  : i32
          %284 = llvm.insertelement %283, %277[%4 : i64] : vector<16xi32>
          %285 = llvm.extractvalue %168[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %286 = llvm.mlir.constant(1 : i64) : i64
          %287 = llvm.extractelement %285[%286 : i64] : vector<4xi32>
          %288 = llvm.mlir.constant(1 : i64) : i64
          %289 = llvm.extractelement %208[%288 : i64] : vector<4xi32>
          %290 = llvm.add %289, %287  : i32
          %291 = llvm.insertelement %290, %284[%5 : i64] : vector<16xi32>
          %292 = llvm.extractvalue %168[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %293 = llvm.mlir.constant(2 : i64) : i64
          %294 = llvm.extractelement %292[%293 : i64] : vector<4xi32>
          %295 = llvm.mlir.constant(2 : i64) : i64
          %296 = llvm.extractelement %208[%295 : i64] : vector<4xi32>
          %297 = llvm.add %296, %294  : i32
          %298 = llvm.insertelement %297, %291[%6 : i64] : vector<16xi32>
          %299 = llvm.extractvalue %168[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %300 = llvm.mlir.constant(3 : i64) : i64
          %301 = llvm.extractelement %299[%300 : i64] : vector<4xi32>
          %302 = llvm.mlir.constant(3 : i64) : i64
          %303 = llvm.extractelement %208[%302 : i64] : vector<4xi32>
          %304 = llvm.add %303, %301  : i32
          %305 = llvm.insertelement %304, %298[%7 : i64] : vector<16xi32>
          %306 = llvm.extractvalue %168[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %307 = llvm.mlir.constant(0 : i64) : i64
          %308 = llvm.extractelement %306[%307 : i64] : vector<4xi32>
          %309 = llvm.mlir.constant(0 : i64) : i64
          %310 = llvm.extractelement %221[%309 : i64] : vector<4xi32>
          %311 = llvm.add %310, %308  : i32
          %312 = llvm.insertelement %311, %305[%8 : i64] : vector<16xi32>
          %313 = llvm.extractvalue %168[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %314 = llvm.mlir.constant(1 : i64) : i64
          %315 = llvm.extractelement %313[%314 : i64] : vector<4xi32>
          %316 = llvm.mlir.constant(1 : i64) : i64
          %317 = llvm.extractelement %221[%316 : i64] : vector<4xi32>
          %318 = llvm.add %317, %315  : i32
          %319 = llvm.insertelement %318, %312[%9 : i64] : vector<16xi32>
          %320 = llvm.extractvalue %168[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %321 = llvm.mlir.constant(2 : i64) : i64
          %322 = llvm.extractelement %320[%321 : i64] : vector<4xi32>
          %323 = llvm.mlir.constant(2 : i64) : i64
          %324 = llvm.extractelement %221[%323 : i64] : vector<4xi32>
          %325 = llvm.add %324, %322  : i32
          %326 = llvm.insertelement %325, %319[%10 : i64] : vector<16xi32>
          %327 = llvm.extractvalue %168[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %328 = llvm.mlir.constant(3 : i64) : i64
          %329 = llvm.extractelement %327[%328 : i64] : vector<4xi32>
          %330 = llvm.mlir.constant(3 : i64) : i64
          %331 = llvm.extractelement %221[%330 : i64] : vector<4xi32>
          %332 = llvm.add %331, %329  : i32
          %333 = llvm.insertelement %332, %326[%11 : i64] : vector<16xi32>
          %334 = llvm.mlir.constant(0 : i64) : i64
          %335 = llvm.extractelement %333[%334 : i64] : vector<16xi32>
          %336 = llvm.extractvalue %15[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %337 = llvm.mlir.constant(0 : i64) : i64
          %338 = llvm.insertelement %335, %336[%337 : i64] : vector<4xi32>
          %339 = llvm.insertvalue %338, %15[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %340 = llvm.mlir.constant(1 : i64) : i64
          %341 = llvm.extractelement %333[%340 : i64] : vector<16xi32>
          %342 = llvm.mlir.constant(1 : i64) : i64
          %343 = llvm.insertelement %341, %338[%342 : i64] : vector<4xi32>
          %344 = llvm.insertvalue %343, %339[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %345 = llvm.mlir.constant(2 : i64) : i64
          %346 = llvm.extractelement %333[%345 : i64] : vector<16xi32>
          %347 = llvm.mlir.constant(2 : i64) : i64
          %348 = llvm.insertelement %346, %343[%347 : i64] : vector<4xi32>
          %349 = llvm.insertvalue %348, %344[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %350 = llvm.mlir.constant(3 : i64) : i64
          %351 = llvm.extractelement %333[%350 : i64] : vector<16xi32>
          %352 = llvm.mlir.constant(3 : i64) : i64
          %353 = llvm.insertelement %351, %348[%352 : i64] : vector<4xi32>
          %354 = llvm.insertvalue %353, %349[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %355 = llvm.mlir.constant(4 : i64) : i64
          %356 = llvm.extractelement %333[%355 : i64] : vector<16xi32>
          %357 = llvm.extractvalue %15[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %358 = llvm.mlir.constant(0 : i64) : i64
          %359 = llvm.insertelement %356, %357[%358 : i64] : vector<4xi32>
          %360 = llvm.insertvalue %359, %354[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %361 = llvm.mlir.constant(5 : i64) : i64
          %362 = llvm.extractelement %333[%361 : i64] : vector<16xi32>
          %363 = llvm.mlir.constant(1 : i64) : i64
          %364 = llvm.insertelement %362, %359[%363 : i64] : vector<4xi32>
          %365 = llvm.insertvalue %364, %360[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %366 = llvm.mlir.constant(6 : i64) : i64
          %367 = llvm.extractelement %333[%366 : i64] : vector<16xi32>
          %368 = llvm.mlir.constant(2 : i64) : i64
          %369 = llvm.insertelement %367, %364[%368 : i64] : vector<4xi32>
          %370 = llvm.insertvalue %369, %365[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %371 = llvm.mlir.constant(7 : i64) : i64
          %372 = llvm.extractelement %333[%371 : i64] : vector<16xi32>
          %373 = llvm.mlir.constant(3 : i64) : i64
          %374 = llvm.insertelement %372, %369[%373 : i64] : vector<4xi32>
          %375 = llvm.insertvalue %374, %370[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %376 = llvm.mlir.constant(8 : i64) : i64
          %377 = llvm.extractelement %333[%376 : i64] : vector<16xi32>
          %378 = llvm.extractvalue %15[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %379 = llvm.mlir.constant(0 : i64) : i64
          %380 = llvm.insertelement %377, %378[%379 : i64] : vector<4xi32>
          %381 = llvm.insertvalue %380, %375[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %382 = llvm.mlir.constant(9 : i64) : i64
          %383 = llvm.extractelement %333[%382 : i64] : vector<16xi32>
          %384 = llvm.mlir.constant(1 : i64) : i64
          %385 = llvm.insertelement %383, %380[%384 : i64] : vector<4xi32>
          %386 = llvm.insertvalue %385, %381[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %387 = llvm.mlir.constant(10 : i64) : i64
          %388 = llvm.extractelement %333[%387 : i64] : vector<16xi32>
          %389 = llvm.mlir.constant(2 : i64) : i64
          %390 = llvm.insertelement %388, %385[%389 : i64] : vector<4xi32>
          %391 = llvm.insertvalue %390, %386[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %392 = llvm.mlir.constant(11 : i64) : i64
          %393 = llvm.extractelement %333[%392 : i64] : vector<16xi32>
          %394 = llvm.mlir.constant(3 : i64) : i64
          %395 = llvm.insertelement %393, %390[%394 : i64] : vector<4xi32>
          %396 = llvm.insertvalue %395, %391[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %397 = llvm.mlir.constant(12 : i64) : i64
          %398 = llvm.extractelement %333[%397 : i64] : vector<16xi32>
          %399 = llvm.extractvalue %15[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %400 = llvm.mlir.constant(0 : i64) : i64
          %401 = llvm.insertelement %398, %399[%400 : i64] : vector<4xi32>
          %402 = llvm.insertvalue %401, %396[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %403 = llvm.mlir.constant(13 : i64) : i64
          %404 = llvm.extractelement %333[%403 : i64] : vector<16xi32>
          %405 = llvm.mlir.constant(1 : i64) : i64
          %406 = llvm.insertelement %404, %401[%405 : i64] : vector<4xi32>
          %407 = llvm.insertvalue %406, %402[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %408 = llvm.mlir.constant(14 : i64) : i64
          %409 = llvm.extractelement %333[%408 : i64] : vector<16xi32>
          %410 = llvm.mlir.constant(2 : i64) : i64
          %411 = llvm.insertelement %409, %406[%410 : i64] : vector<4xi32>
          %412 = llvm.insertvalue %411, %407[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %413 = llvm.mlir.constant(15 : i64) : i64
          %414 = llvm.extractelement %333[%413 : i64] : vector<16xi32>
          %415 = llvm.mlir.constant(3 : i64) : i64
          %416 = llvm.insertelement %414, %411[%415 : i64] : vector<4xi32>
          %417 = llvm.insertvalue %416, %412[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %418 = llvm.add %167, %17  : i64
          llvm.br ^bb4(%418, %417 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %419 = llvm.mlir.constant(256 : index) : i64
          %420 = llvm.mul %120, %419  : i64
          %421 = llvm.add %87, %420  : i64
          %422 = llvm.add %421, %122  : i64
          %423 = llvm.getelementptr %52[%422] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %424 = llvm.bitcast %423 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %425 = llvm.load %424 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %426 = llvm.extractvalue %168[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %427 = llvm.mlir.constant(0 : i64) : i64
          %428 = llvm.extractelement %425[%427 : i64] : vector<4xi32>
          %429 = "llvm.intr.vector.reduce.add"(%426) : (vector<4xi32>) -> i32
          %430 = llvm.add %428, %429  : i32
          %431 = llvm.insertelement %430, %12[%19 : i64] : vector<4xi32>
          %432 = llvm.extractvalue %168[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %433 = llvm.mlir.constant(1 : i64) : i64
          %434 = llvm.extractelement %425[%433 : i64] : vector<4xi32>
          %435 = "llvm.intr.vector.reduce.add"(%432) : (vector<4xi32>) -> i32
          %436 = llvm.add %434, %435  : i32
          %437 = llvm.insertelement %436, %431[%17 : i64] : vector<4xi32>
          %438 = llvm.extractvalue %168[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %439 = llvm.mlir.constant(2 : i64) : i64
          %440 = llvm.extractelement %425[%439 : i64] : vector<4xi32>
          %441 = "llvm.intr.vector.reduce.add"(%438) : (vector<4xi32>) -> i32
          %442 = llvm.add %440, %441  : i32
          %443 = llvm.insertelement %442, %437[%13 : i64] : vector<4xi32>
          %444 = llvm.extractvalue %168[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %445 = llvm.mlir.constant(3 : i64) : i64
          %446 = llvm.extractelement %425[%445 : i64] : vector<4xi32>
          %447 = "llvm.intr.vector.reduce.add"(%444) : (vector<4xi32>) -> i32
          %448 = llvm.add %446, %447  : i32
          %449 = llvm.insertelement %448, %443[%14 : i64] : vector<4xi32>
          %450 = llvm.mlir.constant(256 : index) : i64
          %451 = llvm.mul %120, %450  : i64
          %452 = llvm.add %87, %451  : i64
          %453 = llvm.add %452, %122  : i64
          %454 = llvm.getelementptr %52[%453] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %455 = llvm.bitcast %454 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          llvm.store %449, %455 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %456 = llvm.add %122, %16  : i64
          llvm.br ^bb2(%456 : i64)
        ^bb7:  // pred: ^bb2
          %457 = llvm.add %120, %17  : i64
          llvm.br ^bb1(%457 : i64)
        ^bb8:  // pred: ^bb1
          %458 = llvm.mlir.constant(0 : i32) : i32
          llvm.return %458 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %62 = llvm.extractvalue %61[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %63 = llvm.zext %62 : i32 to i64
          %64 = llvm.mul %63, %41  : i64
          %65 = llvm.mul %60, %41  : i64
          %66 = llvm.mul %64, %20  : i64
          %67 = llvm.add %66, %42  : i64
          %68 = llvm.mul %65, %40  : i64
          %69 = llvm.add %67, %68  : i64
          %70 = llvm.mul %64, %21  : i64
          %71 = llvm.add %70, %42  : i64
          %72 = llvm.mul %65, %19  : i64
          %73 = llvm.add %71, %72  : i64
          %74 = llvm.mul %22, %40  : i64
          %75 = llvm.add %73, %74  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%76: i64):  // 2 preds: ^bb0, ^bb7
          %77 = llvm.icmp "slt" %76, %41 : i64
          llvm.cond_br %77, ^bb2(%42 : i64), ^bb8
        ^bb2(%78: i64):  // 2 preds: ^bb1, ^bb6
          %79 = llvm.icmp "slt" %78, %41 : i64
          llvm.cond_br %79, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %80 = llvm.mul %76, %15  : i64
          %81 = llvm.add %75, %80  : i64
          %82 = llvm.mul %78, %16  : i64
          %83 = llvm.add %81, %82  : i64
          %84 = llvm.mul %22, %17  : i64
          %85 = llvm.add %83, %84  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%86: i64, %87: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %88 = llvm.icmp "slt" %86, %41 : i64
          llvm.cond_br %88, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %89 = llvm.mul %42, %21  : i64
          %90 = llvm.add %85, %89  : i64
          %91 = llvm.mul %42, %19  : i64
          %92 = llvm.add %90, %91  : i64
          %93 = llvm.mul %86, %39  : i64
          %94 = llvm.add %92, %93  : i64
          %95 = llvm.add %94, %42  : i64
          %96 = llvm.getelementptr %46[%95] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %97 = llvm.bitcast %96 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %98 = llvm.load %97 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %99 = llvm.mul %42, %21  : i64
          %100 = llvm.add %85, %99  : i64
          %101 = llvm.mul %40, %19  : i64
          %102 = llvm.add %100, %101  : i64
          %103 = llvm.mul %86, %39  : i64
          %104 = llvm.add %102, %103  : i64
          %105 = llvm.add %104, %42  : i64
          %106 = llvm.getelementptr %46[%105] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %107 = llvm.bitcast %106 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %108 = llvm.load %107 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %109 = llvm.mul %42, %21  : i64
          %110 = llvm.add %85, %109  : i64
          %111 = llvm.mul %36, %19  : i64
          %112 = llvm.add %110, %111  : i64
          %113 = llvm.mul %86, %39  : i64
          %114 = llvm.add %112, %113  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.mul %42, %21  : i64
          %120 = llvm.add %85, %119  : i64
          %121 = llvm.mul %37, %19  : i64
          %122 = llvm.add %120, %121  : i64
          %123 = llvm.mul %86, %39  : i64
          %124 = llvm.add %122, %123  : i64
          %125 = llvm.add %124, %42  : i64
          %126 = llvm.getelementptr %46[%125] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %127 = llvm.bitcast %126 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %128 = llvm.load %127 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %129 = llvm.extractvalue %87[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %130 = llvm.extractelement %129[%22 : i64] : vector<4xi32>
          %131 = llvm.extractelement %98[%22 : i64] : vector<4xi32>
          %132 = llvm.add %131, %130  : i32
          %133 = llvm.insertelement %132, %23[%42 : i64] : vector<16xi32>
          %134 = llvm.extractvalue %87[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %135 = llvm.extractelement %134[%17 : i64] : vector<4xi32>
          %136 = llvm.extractelement %98[%17 : i64] : vector<4xi32>
          %137 = llvm.add %136, %135  : i32
          %138 = llvm.insertelement %137, %133[%40 : i64] : vector<16xi32>
          %139 = llvm.extractvalue %87[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %140 = llvm.extractelement %139[%13 : i64] : vector<4xi32>
          %141 = llvm.extractelement %98[%13 : i64] : vector<4xi32>
          %142 = llvm.add %141, %140  : i32
          %143 = llvm.insertelement %142, %138[%36 : i64] : vector<16xi32>
          %144 = llvm.extractvalue %87[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %145 = llvm.extractelement %144[%12 : i64] : vector<4xi32>
          %146 = llvm.extractelement %98[%12 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %143[%37 : i64] : vector<16xi32>
          %149 = llvm.extractvalue %87[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %150 = llvm.extractelement %149[%22 : i64] : vector<4xi32>
          %151 = llvm.extractelement %108[%22 : i64] : vector<4xi32>
          %152 = llvm.add %151, %150  : i32
          %153 = llvm.insertelement %152, %148[%39 : i64] : vector<16xi32>
          %154 = llvm.extractvalue %87[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %155 = llvm.extractelement %154[%17 : i64] : vector<4xi32>
          %156 = llvm.extractelement %108[%17 : i64] : vector<4xi32>
          %157 = llvm.add %156, %155  : i32
          %158 = llvm.insertelement %157, %153[%24 : i64] : vector<16xi32>
          %159 = llvm.extractvalue %87[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %160 = llvm.extractelement %159[%13 : i64] : vector<4xi32>
          %161 = llvm.extractelement %108[%13 : i64] : vector<4xi32>
          %162 = llvm.add %161, %160  : i32
          %163 = llvm.insertelement %162, %158[%25 : i64] : vector<16xi32>
          %164 = llvm.extractvalue %87[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %165 = llvm.extractelement %164[%12 : i64] : vector<4xi32>
          %166 = llvm.extractelement %108[%12 : i64] : vector<4xi32>
          %167 = llvm.add %166, %165  : i32
          %168 = llvm.insertelement %167, %163[%26 : i64] : vector<16xi32>
          %169 = llvm.extractvalue %87[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %170 = llvm.extractelement %169[%22 : i64] : vector<4xi32>
          %171 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %172 = llvm.add %171, %170  : i32
          %173 = llvm.insertelement %172, %168[%27 : i64] : vector<16xi32>
          %174 = llvm.extractvalue %87[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %175 = llvm.extractelement %174[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %173[%28 : i64] : vector<16xi32>
          %179 = llvm.extractvalue %87[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %180 = llvm.extractelement %179[%13 : i64] : vector<4xi32>
          %181 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %182 = llvm.add %181, %180  : i32
          %183 = llvm.insertelement %182, %178[%29 : i64] : vector<16xi32>
          %184 = llvm.extractvalue %87[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %185 = llvm.extractelement %184[%12 : i64] : vector<4xi32>
          %186 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %187 = llvm.add %186, %185  : i32
          %188 = llvm.insertelement %187, %183[%30 : i64] : vector<16xi32>
          %189 = llvm.extractvalue %87[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %190 = llvm.extractelement %189[%22 : i64] : vector<4xi32>
          %191 = llvm.extractelement %128[%22 : i64] : vector<4xi32>
          %192 = llvm.add %191, %190  : i32
          %193 = llvm.insertelement %192, %188[%31 : i64] : vector<16xi32>
          %194 = llvm.extractvalue %87[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %195 = llvm.extractelement %194[%17 : i64] : vector<4xi32>
          %196 = llvm.extractelement %128[%17 : i64] : vector<4xi32>
          %197 = llvm.add %196, %195  : i32
          %198 = llvm.insertelement %197, %193[%32 : i64] : vector<16xi32>
          %199 = llvm.extractvalue %87[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %199[%13 : i64] : vector<4xi32>
          %201 = llvm.extractelement %128[%13 : i64] : vector<4xi32>
          %202 = llvm.add %201, %200  : i32
          %203 = llvm.insertelement %202, %198[%33 : i64] : vector<16xi32>
          %204 = llvm.extractvalue %87[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %205 = llvm.extractelement %204[%12 : i64] : vector<4xi32>
          %206 = llvm.extractelement %128[%12 : i64] : vector<4xi32>
          %207 = llvm.add %206, %205  : i32
          %208 = llvm.insertelement %207, %203[%34 : i64] : vector<16xi32>
          %209 = llvm.extractelement %208[%22 : i64] : vector<16xi32>
          %210 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %211 = llvm.insertelement %209, %210[%22 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %208[%17 : i64] : vector<16xi32>
          %214 = llvm.insertelement %213, %211[%17 : i64] : vector<4xi32>
          %215 = llvm.insertvalue %214, %212[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %216 = llvm.extractelement %208[%13 : i64] : vector<16xi32>
          %217 = llvm.insertelement %216, %214[%13 : i64] : vector<4xi32>
          %218 = llvm.insertvalue %217, %215[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %219 = llvm.extractelement %208[%12 : i64] : vector<16xi32>
          %220 = llvm.insertelement %219, %217[%12 : i64] : vector<4xi32>
          %221 = llvm.insertvalue %220, %218[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %222 = llvm.extractelement %208[%14 : i64] : vector<16xi32>
          %223 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %224 = llvm.insertelement %222, %223[%22 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %221[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %208[%11 : i64] : vector<16xi32>
          %227 = llvm.insertelement %226, %224[%17 : i64] : vector<4xi32>
          %228 = llvm.insertvalue %227, %225[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %229 = llvm.extractelement %208[%10 : i64] : vector<16xi32>
          %230 = llvm.insertelement %229, %227[%13 : i64] : vector<4xi32>
          %231 = llvm.insertvalue %230, %228[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %232 = llvm.extractelement %208[%9 : i64] : vector<16xi32>
          %233 = llvm.insertelement %232, %230[%12 : i64] : vector<4xi32>
          %234 = llvm.insertvalue %233, %231[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %235 = llvm.extractelement %208[%8 : i64] : vector<16xi32>
          %236 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %237 = llvm.insertelement %235, %236[%22 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %234[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.extractelement %208[%7 : i64] : vector<16xi32>
          %240 = llvm.insertelement %239, %237[%17 : i64] : vector<4xi32>
          %241 = llvm.insertvalue %240, %238[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %242 = llvm.extractelement %208[%6 : i64] : vector<16xi32>
          %243 = llvm.insertelement %242, %240[%13 : i64] : vector<4xi32>
          %244 = llvm.insertvalue %243, %241[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %245 = llvm.extractelement %208[%5 : i64] : vector<16xi32>
          %246 = llvm.insertelement %245, %243[%12 : i64] : vector<4xi32>
          %247 = llvm.insertvalue %246, %244[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %248 = llvm.extractelement %208[%4 : i64] : vector<16xi32>
          %249 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %250 = llvm.insertelement %248, %249[%22 : i64] : vector<4xi32>
          %251 = llvm.insertvalue %250, %247[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %208[%3 : i64] : vector<16xi32>
          %253 = llvm.insertelement %252, %250[%17 : i64] : vector<4xi32>
          %254 = llvm.insertvalue %253, %251[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %255 = llvm.extractelement %208[%2 : i64] : vector<16xi32>
          %256 = llvm.insertelement %255, %253[%13 : i64] : vector<4xi32>
          %257 = llvm.insertvalue %256, %254[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %258 = llvm.extractelement %208[%1 : i64] : vector<16xi32>
          %259 = llvm.insertelement %258, %256[%12 : i64] : vector<4xi32>
          %260 = llvm.insertvalue %259, %257[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %261 = llvm.add %86, %40  : i64
          llvm.br ^bb4(%261, %260 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %262 = llvm.mul %76, %20  : i64
          %263 = llvm.add %69, %262  : i64
          %264 = llvm.add %263, %78  : i64
          %265 = llvm.getelementptr %54[%264] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %266 = llvm.bitcast %265 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %267 = llvm.load %266 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %268 = llvm.extractvalue %87[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %269 = llvm.extractelement %267[%22 : i64] : vector<4xi32>
          %270 = "llvm.intr.vector.reduce.add"(%268) : (vector<4xi32>) -> i32
          %271 = llvm.add %269, %270  : i32
          %272 = llvm.insertelement %271, %35[%42 : i64] : vector<4xi32>
          %273 = llvm.extractvalue %87[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %274 = llvm.extractelement %267[%17 : i64] : vector<4xi32>
          %275 = "llvm.intr.vector.reduce.add"(%273) : (vector<4xi32>) -> i32
          %276 = llvm.add %274, %275  : i32
          %277 = llvm.insertelement %276, %272[%40 : i64] : vector<4xi32>
          %278 = llvm.extractvalue %87[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %279 = llvm.extractelement %267[%13 : i64] : vector<4xi32>
          %280 = "llvm.intr.vector.reduce.add"(%278) : (vector<4xi32>) -> i32
          %281 = llvm.add %279, %280  : i32
          %282 = llvm.insertelement %281, %277[%36 : i64] : vector<4xi32>
          %283 = llvm.extractvalue %87[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %284 = llvm.extractelement %267[%12 : i64] : vector<4xi32>
          %285 = "llvm.intr.vector.reduce.add"(%283) : (vector<4xi32>) -> i32
          %286 = llvm.add %284, %285  : i32
          %287 = llvm.insertelement %286, %282[%37 : i64] : vector<4xi32>
          %288 = llvm.mul %76, %20  : i64
          %289 = llvm.add %69, %288  : i64
          %290 = llvm.add %289, %78  : i64
          %291 = llvm.getelementptr %54[%290] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %292 = llvm.bitcast %291 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          llvm.store %287, %292 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %293 = llvm.add %78, %39  : i64
          llvm.br ^bb2(%293 : i64)
        ^bb7:  // pred: ^bb2
          %294 = llvm.add %76, %40  : i64
          llvm.br ^bb1(%294 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After CSE (cse) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::TranslateTargetExecutableVariantsPass (iree-hal-translate-target-executable-variants) ('hal.executable.variant' operation: @embedded_elf_x86_64) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::TranslateExecutablesPass (iree-hal-translate-executables) ('hal.executable' operation: @_split_reduction_pass2_dispatch_0) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %0 = stream.resource.alloc uninitialized : !stream.resource<transient>{%c67108864}
    %1 = stream.cmd.execute with(%0 as %arg0: !stream.resource<transient>{%c67108864}) {
      stream.cmd.fill %c1_i32, %arg0[%c0 for %c67108864] : i32 -> !stream.resource<transient>{%c67108864}
    } => !stream.timepoint
    %2 = stream.timepoint.await %1 => %0 : !stream.resource<transient>{%c67108864}
    %3 = util.do_not_optimize(%2) : !stream.resource<transient>
    %4 = stream.resource.size %3 : !stream.resource<transient>
    %5 = stream.resource.alloc uninitialized : !stream.resource<external>{%c1048576}
    %6 = stream.cmd.execute with(%3 as %arg0: !stream.resource<transient>{%4}, %5 as %arg1: !stream.resource<external>{%c1048576}) {
      stream.cmd.concurrent {
        stream.cmd.dispatch @_split_reduction_pass2_dispatch_0::@_split_reduction_pass2_dispatch_0_generic_512x256x128[%c512, %c256, %c1] {
          ro %arg0[%c0 for %4] : !stream.resource<transient>{%4},
          wo %arg1[%c0 for %c1048576] : !stream.resource<external>{%c1048576}
        } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>]}
        stream.cmd.fill %c128_i32, %arg1[%c524288 for %c524288] : i32 -> !stream.resource<external>{%c1048576}
      }
    } => !stream.timepoint
    %7 = stream.timepoint.await %6 => %5 : !stream.resource<external>{%c1048576}
    %8 = stream.resource.subview %7[%c0] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %9 = stream.resource.subview %7[%c524288] : !stream.resource<external>{%c1048576} -> !stream.resource<external>{%c524288}
    %10 = stream.tensor.export %8 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    %11 = stream.tensor.export %9 : tensor<512x256xi32> in !stream.resource<external>{%c524288} -> tensor<512x256xi32>
    check.expect_eq(%10, %11) : tensor<512x256xi32>
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::(anonymous namespace)::ConvertToHALPass (iree-hal-conversion) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %device_0 = hal.ex.shared_device : !hal.device
    %cmd = hal.command_buffer.create device(%device_0 : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device_0 : !hal.device) flags("None") : !hal.fence
    %c-1_i64 = arith.constant -1 : i64
    hal.device.queue.execute<%device_0 : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %c-1_i32 = arith.constant -1 : i32
    %status = hal.fence.await until([%fence]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %device_1 = hal.ex.shared_device : !hal.device
    %allocator_2 = hal.device.allocator<%device_1 : !hal.device> : !hal.allocator
    %buffer_3 = hal.allocator.allocate<%allocator_2 : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %device_4 = hal.ex.shared_device : !hal.device
    %cmd_5 = hal.command_buffer.create device(%device_4 : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    %2 = hal.command_buffer.device<%cmd_5 : !hal.command_buffer> : !hal.device
    hal.device.switch<%2 : !hal.device>
    #hal.device.match.executable.format<"embedded-elf-x86_64"> {
      %pipeline_layout = hal.pipeline_layout.lookup device(%2 : !hal.device) layout(#pipeline_layout) : !hal.pipeline_layout
      %c0_22 = arith.constant 0 : index
      %c1_23 = arith.constant 1 : index
      %c0_24 = arith.constant 0 : index
      hal.command_buffer.push_descriptor_set<%cmd_5 : !hal.command_buffer> layout(%pipeline_layout : !hal.pipeline_layout)[%c0_24] bindings([
        %c0_22 = (%1 : !hal.buffer)[%c0, %len], 
        %c1_23 = (%buffer_3 : !hal.buffer)[%c0, %c1048576]
      ])
      %c1_25 = arith.constant 1 : index
      %c16 = arith.constant 16 : index
      %c8 = arith.constant 8 : index
      hal.command_buffer.dispatch.symbol<%cmd_5 : !hal.command_buffer> target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64::@_split_reduction_pass2_dispatch_0_generic_512x256x128) workgroups([%c8, %c16, %c1_25])
      hal.return
    }
    hal.command_buffer.fill_buffer<%cmd_5 : !hal.command_buffer> target(%buffer_3 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_5 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_5 : !hal.command_buffer>
    %3 = util.null : !hal.fence
    %fence_6 = hal.fence.create device(%device_4 : !hal.device) flags("None") : !hal.fence
    %c-1_i64_7 = arith.constant -1 : i64
    hal.device.queue.execute<%device_4 : !hal.device> affinity(%c-1_i64_7) wait(%3) signal(%fence_6) commands([%cmd_5])
    %c-1_i32_8 = arith.constant -1 : i32
    %status_9 = hal.fence.await until([%fence_6]) timeout_millis(%c-1_i32_8) : i32
    util.status.check_ok %status_9, "failed to wait on timepoint"
    %buffer_10 = hal.buffer.subspan<%buffer_3 : !hal.buffer>[%c0, %c524288] : !hal.buffer
    %buffer_11 = hal.buffer.subspan<%buffer_3 : !hal.buffer>[%c524288, %c524288] : !hal.buffer
    %c512_12 = arith.constant 512 : index
    %c256_13 = arith.constant 256 : index
    %c0_14 = arith.constant 0 : index
    %c268435488_i32 = arith.constant 268435488 : i32
    %c1_i32_15 = arith.constant 1 : i32
    %view = hal.buffer_view.create buffer(%buffer_10 : !hal.buffer)[%c0_14, %c524288] shape([%c512_12, %c256_13]) type(%c268435488_i32) encoding(%c1_i32_15) : !hal.buffer_view
    %c512_16 = arith.constant 512 : index
    %c256_17 = arith.constant 256 : index
    %c0_18 = arith.constant 0 : index
    %c268435488_i32_19 = arith.constant 268435488 : i32
    %c1_i32_20 = arith.constant 1 : i32
    %view_21 = hal.buffer_view.create buffer(%buffer_11 : !hal.buffer)[%c0_18, %c524288] shape([%c512_16, %c256_17]) type(%c268435488_i32_19) encoding(%c1_i32_20) : !hal.buffer_view
    check.expect_eq(%view, %view_21) : !hal.buffer_view
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::FixupLegacySyncPass (iree-hal-fixup-legacy-sync) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %device_0 = hal.ex.shared_device : !hal.device
    %cmd = hal.command_buffer.create device(%device_0 : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device_0 : !hal.device) flags("None") : !hal.fence
    %c-1_i64 = arith.constant -1 : i64
    %c-1_i32 = arith.constant -1 : i32
    %status = hal.fence.await until([%0]) timeout_millis(%c-1_i32) : i32
    hal.device.queue.execute<%device_0 : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %c-1_i32_1 = arith.constant -1 : i32
    %status_2 = hal.fence.await until([%fence]) timeout_millis(%c-1_i32_1) : i32
    util.status.check_ok %status_2, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %device_3 = hal.ex.shared_device : !hal.device
    %allocator_4 = hal.device.allocator<%device_3 : !hal.device> : !hal.allocator
    %buffer_5 = hal.allocator.allocate<%allocator_4 : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %device_6 = hal.ex.shared_device : !hal.device
    %cmd_7 = hal.command_buffer.create device(%device_6 : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    %2 = hal.command_buffer.device<%cmd_7 : !hal.command_buffer> : !hal.device
    hal.device.switch<%2 : !hal.device>
    #hal.device.match.executable.format<"embedded-elf-x86_64"> {
      %pipeline_layout = hal.pipeline_layout.lookup device(%2 : !hal.device) layout(#pipeline_layout) : !hal.pipeline_layout
      %c0_26 = arith.constant 0 : index
      %c1_27 = arith.constant 1 : index
      %c0_28 = arith.constant 0 : index
      hal.command_buffer.push_descriptor_set<%cmd_7 : !hal.command_buffer> layout(%pipeline_layout : !hal.pipeline_layout)[%c0_28] bindings([
        %c0_26 = (%1 : !hal.buffer)[%c0, %len], 
        %c1_27 = (%buffer_5 : !hal.buffer)[%c0, %c1048576]
      ])
      %c1_29 = arith.constant 1 : index
      %c16 = arith.constant 16 : index
      %c8 = arith.constant 8 : index
      hal.command_buffer.dispatch.symbol<%cmd_7 : !hal.command_buffer> target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64::@_split_reduction_pass2_dispatch_0_generic_512x256x128) workgroups([%c8, %c16, %c1_29])
      hal.return
    }
    hal.command_buffer.fill_buffer<%cmd_7 : !hal.command_buffer> target(%buffer_5 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_7 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_7 : !hal.command_buffer>
    %3 = util.null : !hal.fence
    %fence_8 = hal.fence.create device(%device_6 : !hal.device) flags("None") : !hal.fence
    %c-1_i64_9 = arith.constant -1 : i64
    %c-1_i32_10 = arith.constant -1 : i32
    %status_11 = hal.fence.await until([%3]) timeout_millis(%c-1_i32_10) : i32
    hal.device.queue.execute<%device_6 : !hal.device> affinity(%c-1_i64_9) wait(%3) signal(%fence_8) commands([%cmd_7])
    %c-1_i32_12 = arith.constant -1 : i32
    %status_13 = hal.fence.await until([%fence_8]) timeout_millis(%c-1_i32_12) : i32
    util.status.check_ok %status_13, "failed to wait on timepoint"
    %buffer_14 = hal.buffer.subspan<%buffer_5 : !hal.buffer>[%c0, %c524288] : !hal.buffer
    %buffer_15 = hal.buffer.subspan<%buffer_5 : !hal.buffer>[%c524288, %c524288] : !hal.buffer
    %c512_16 = arith.constant 512 : index
    %c256_17 = arith.constant 256 : index
    %c0_18 = arith.constant 0 : index
    %c268435488_i32 = arith.constant 268435488 : i32
    %c1_i32_19 = arith.constant 1 : i32
    %view = hal.buffer_view.create buffer(%buffer_14 : !hal.buffer)[%c0_18, %c524288] shape([%c512_16, %c256_17]) type(%c268435488_i32) encoding(%c1_i32_19) : !hal.buffer_view
    %c512_20 = arith.constant 512 : index
    %c256_21 = arith.constant 256 : index
    %c0_22 = arith.constant 0 : index
    %c268435488_i32_23 = arith.constant 268435488 : i32
    %c1_i32_24 = arith.constant 1 : i32
    %view_25 = hal.buffer_view.create buffer(%buffer_15 : !hal.buffer)[%c0_22, %c524288] shape([%c512_20, %c256_21]) type(%c268435488_i32_23) encoding(%c1_i32_24) : !hal.buffer_view
    check.expect_eq(%view, %view_25) : !hal.buffer_view
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c268435488_i32 = arith.constant 268435488 : i32
    %c8 = arith.constant 8 : index
    %c16 = arith.constant 16 : index
    %c-1_i32 = arith.constant -1 : i32
    %c-1_i64 = arith.constant -1 : i64
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %device_0 = hal.ex.shared_device : !hal.device
    %cmd = hal.command_buffer.create device(%device_0 : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device_0 : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device_0 : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %status = hal.fence.await until([%fence]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %device_1 = hal.ex.shared_device : !hal.device
    %allocator_2 = hal.device.allocator<%device_1 : !hal.device> : !hal.allocator
    %buffer_3 = hal.allocator.allocate<%allocator_2 : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %device_4 = hal.ex.shared_device : !hal.device
    %cmd_5 = hal.command_buffer.create device(%device_4 : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    hal.device.switch<%device_4 : !hal.device>
    #hal.device.match.executable.format<"embedded-elf-x86_64"> {
      %pipeline_layout = hal.pipeline_layout.lookup device(%device_4 : !hal.device) layout(#pipeline_layout) : !hal.pipeline_layout
      hal.command_buffer.push_descriptor_set<%cmd_5 : !hal.command_buffer> layout(%pipeline_layout : !hal.pipeline_layout)[%c0] bindings([
        %c0 = (%1 : !hal.buffer)[%c0, %len], 
        %c1 = (%buffer_3 : !hal.buffer)[%c0, %c1048576]
      ])
      hal.command_buffer.dispatch.symbol<%cmd_5 : !hal.command_buffer> target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64::@_split_reduction_pass2_dispatch_0_generic_512x256x128) workgroups([%c8, %c16, %c1])
      hal.return
    }
    hal.command_buffer.fill_buffer<%cmd_5 : !hal.command_buffer> target(%buffer_3 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_5 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_5 : !hal.command_buffer>
    %2 = util.null : !hal.fence
    %fence_6 = hal.fence.create device(%device_4 : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device_4 : !hal.device> affinity(%c-1_i64) wait(%2) signal(%fence_6) commands([%cmd_5])
    %status_7 = hal.fence.await until([%fence_6]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status_7, "failed to wait on timepoint"
    %view = hal.buffer_view.create buffer(%buffer_3 : !hal.buffer)[%c0, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    %view_8 = hal.buffer_view.create buffer(%buffer_3 : !hal.buffer)[%c524288, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    check.expect_eq(%view, %view_8) : !hal.buffer_view
    return
  }
}


// -----// IR Dump After CSE (cse) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c268435488_i32 = arith.constant 268435488 : i32
    %c8 = arith.constant 8 : index
    %c16 = arith.constant 16 : index
    %c-1_i32 = arith.constant -1 : i32
    %c-1_i64 = arith.constant -1 : i64
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %cmd = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %status = hal.fence.await until([%fence]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %buffer_0 = hal.allocator.allocate<%allocator : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %cmd_1 = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    hal.device.switch<%device : !hal.device>
    #hal.device.match.executable.format<"embedded-elf-x86_64"> {
      %pipeline_layout = hal.pipeline_layout.lookup device(%device : !hal.device) layout(#pipeline_layout) : !hal.pipeline_layout
      hal.command_buffer.push_descriptor_set<%cmd_1 : !hal.command_buffer> layout(%pipeline_layout : !hal.pipeline_layout)[%c0] bindings([
        %c0 = (%1 : !hal.buffer)[%c0, %len], 
        %c1 = (%buffer_0 : !hal.buffer)[%c0, %c1048576]
      ])
      hal.command_buffer.dispatch.symbol<%cmd_1 : !hal.command_buffer> target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64::@_split_reduction_pass2_dispatch_0_generic_512x256x128) workgroups([%c8, %c16, %c1])
      hal.return
    }
    hal.command_buffer.fill_buffer<%cmd_1 : !hal.command_buffer> target(%buffer_0 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_1 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_1 : !hal.command_buffer>
    %fence_2 = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence_2) commands([%cmd_1])
    %status_3 = hal.fence.await until([%fence_2]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status_3, "failed to wait on timepoint"
    %view = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c0, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    %view_4 = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c524288, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    check.expect_eq(%view, %view_4) : !hal.buffer_view
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::ResolveExportOrdinalsPass (iree-hal-resolve-export-ordinals) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c268435488_i32 = arith.constant 268435488 : i32
    %c8 = arith.constant 8 : index
    %c16 = arith.constant 16 : index
    %c-1_i32 = arith.constant -1 : i32
    %c-1_i64 = arith.constant -1 : i64
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %cmd = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %status = hal.fence.await until([%fence]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %buffer_0 = hal.allocator.allocate<%allocator : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %cmd_1 = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    hal.device.switch<%device : !hal.device>
    #hal.device.match.executable.format<"embedded-elf-x86_64"> {
      %pipeline_layout = hal.pipeline_layout.lookup device(%device : !hal.device) layout(#pipeline_layout) : !hal.pipeline_layout
      hal.command_buffer.push_descriptor_set<%cmd_1 : !hal.command_buffer> layout(%pipeline_layout : !hal.pipeline_layout)[%c0] bindings([
        %c0 = (%1 : !hal.buffer)[%c0, %len], 
        %c1 = (%buffer_0 : !hal.buffer)[%c0, %c1048576]
      ])
      %2 = hal.command_buffer.device<%cmd_1 : !hal.command_buffer> : !hal.device
      %exe = hal.executable.lookup device(%2 : !hal.device) executable(@_split_reduction_pass2_dispatch_0) : !hal.executable
      hal.command_buffer.dispatch<%cmd_1 : !hal.command_buffer> target(%exe : !hal.executable)[0] workgroups([%c8, %c16, %c1])
      hal.return
    }
    hal.command_buffer.fill_buffer<%cmd_1 : !hal.command_buffer> target(%buffer_0 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_1 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_1 : !hal.command_buffer>
    %fence_2 = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence_2) commands([%cmd_1])
    %status_3 = hal.fence.await until([%fence_2]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status_3, "failed to wait on timepoint"
    %view = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c0, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    %view_4 = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c524288, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    check.expect_eq(%view, %view_4) : !hal.buffer_view
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::MaterializeResourceCachesPass (iree-hal-materialize-resource-caches) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  util.global private @_descriptor_set_layout_0 : !hal.descriptor_set_layout
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %descriptor_set_layout = hal.descriptor_set_layout.create device(%device : !hal.device) flags("None") bindings([#hal.descriptor_set.binding<0, storage_buffer, ReadOnly>, #hal.descriptor_set.binding<1, storage_buffer>]) : !hal.descriptor_set_layout
    util.global.store %descriptor_set_layout, @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    util.initializer.return
  }
  util.global private @_pipeline_layout_0 : !hal.pipeline_layout
  util.initializer {
    %_descriptor_set_layout_0 = util.global.load @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    %device = hal.ex.shared_device : !hal.device
    %pipeline_layout = hal.pipeline_layout.create device(%device : !hal.device) push_constants(0) layouts([%_descriptor_set_layout_0]) : !hal.pipeline_layout
    util.global.store %pipeline_layout, @_pipeline_layout_0 : !hal.pipeline_layout
    util.initializer.return
  }
  util.global private @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %0 = hal.device.switch<%device : !hal.device> -> !hal.executable
    #hal.device.match.executable.format<"embedded-elf-x86_64"> {
      %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
      %exe = hal.executable.create device(%device : !hal.device) target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64) layouts([%_pipeline_layout_0]) : !hal.executable
      hal.return %exe : !hal.executable
    },
    #hal.match.always {
      %1 = util.null : !hal.executable
      hal.return %1 : !hal.executable
    }
    util.global.store %0, @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    util.initializer.return
  }
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c268435488_i32 = arith.constant 268435488 : i32
    %c8 = arith.constant 8 : index
    %c16 = arith.constant 16 : index
    %c-1_i32 = arith.constant -1 : i32
    %c-1_i64 = arith.constant -1 : i64
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %cmd = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %status = hal.fence.await until([%fence]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %buffer_0 = hal.allocator.allocate<%allocator : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %cmd_1 = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    hal.device.switch<%device : !hal.device>
    #hal.device.match.executable.format<"embedded-elf-x86_64"> {
      %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
      hal.command_buffer.push_descriptor_set<%cmd_1 : !hal.command_buffer> layout(%_pipeline_layout_0 : !hal.pipeline_layout)[%c0] bindings([
        %c0 = (%1 : !hal.buffer)[%c0, %len], 
        %c1 = (%buffer_0 : !hal.buffer)[%c0, %c1048576]
      ])
      %2 = hal.command_buffer.device<%cmd_1 : !hal.command_buffer> : !hal.device
      %_executable__split_reduction_pass2_dispatch_0 = util.global.load @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
      hal.command_buffer.dispatch<%cmd_1 : !hal.command_buffer> target(%_executable__split_reduction_pass2_dispatch_0 : !hal.executable)[0] workgroups([%c8, %c16, %c1])
      hal.return
    }
    hal.command_buffer.fill_buffer<%cmd_1 : !hal.command_buffer> target(%buffer_0 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_1 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_1 : !hal.command_buffer>
    %fence_2 = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence_2) commands([%cmd_1])
    %status_3 = hal.fence.await until([%fence_2]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status_3, "failed to wait on timepoint"
    %view = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c0, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    %view_4 = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c524288, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    check.expect_eq(%view, %view_4) : !hal.buffer_view
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::InlineDeviceSwitchesPass (iree-hal-inline-device-switches) ('util.initializer' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  util.global private @_descriptor_set_layout_0 : !hal.descriptor_set_layout
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %descriptor_set_layout = hal.descriptor_set_layout.create device(%device : !hal.device) flags("None") bindings([#hal.descriptor_set.binding<0, storage_buffer, ReadOnly>, #hal.descriptor_set.binding<1, storage_buffer>]) : !hal.descriptor_set_layout
    util.global.store %descriptor_set_layout, @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    util.initializer.return
  }
  util.global private @_pipeline_layout_0 : !hal.pipeline_layout
  util.initializer {
    %_descriptor_set_layout_0 = util.global.load @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    %device = hal.ex.shared_device : !hal.device
    %pipeline_layout = hal.pipeline_layout.create device(%device : !hal.device) push_constants(0) layouts([%_descriptor_set_layout_0]) : !hal.pipeline_layout
    util.global.store %pipeline_layout, @_pipeline_layout_0 : !hal.pipeline_layout
    util.initializer.return
  }
  util.global private @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %ok, %value = hal.device.query<%device : !hal.device> key("hal.executable.format" :: "embedded-elf-x86_64") : i1, i1 = false
    cf.cond_br %value, ^bb1, ^bb2
  ^bb1:  // pred: ^bb0
    %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
    %exe = hal.executable.create device(%device : !hal.device) target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64) layouts([%_pipeline_layout_0]) : !hal.executable
    cf.br ^bb5(%exe : !hal.executable)
  ^bb2:  // pred: ^bb0
    %true = arith.constant true
    cf.cond_br %true, ^bb3, ^bb4
  ^bb3:  // pred: ^bb2
    %0 = util.null : !hal.executable
    cf.br ^bb5(%0 : !hal.executable)
  ^bb4:  // pred: ^bb2
    util.unreachable "device not supported in the compiled configuration"
  ^bb5(%1: !hal.executable):  // 2 preds: ^bb1, ^bb3
    util.global.store %1, @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    util.initializer.return
  }
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c268435488_i32 = arith.constant 268435488 : i32
    %c8 = arith.constant 8 : index
    %c16 = arith.constant 16 : index
    %c-1_i32 = arith.constant -1 : i32
    %c-1_i64 = arith.constant -1 : i64
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %cmd = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %status = hal.fence.await until([%fence]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %buffer_0 = hal.allocator.allocate<%allocator : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %cmd_1 = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    hal.device.switch<%device : !hal.device>
    #hal.device.match.executable.format<"embedded-elf-x86_64"> {
      %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
      hal.command_buffer.push_descriptor_set<%cmd_1 : !hal.command_buffer> layout(%_pipeline_layout_0 : !hal.pipeline_layout)[%c0] bindings([
        %c0 = (%1 : !hal.buffer)[%c0, %len], 
        %c1 = (%buffer_0 : !hal.buffer)[%c0, %c1048576]
      ])
      %2 = hal.command_buffer.device<%cmd_1 : !hal.command_buffer> : !hal.device
      %_executable__split_reduction_pass2_dispatch_0 = util.global.load @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
      hal.command_buffer.dispatch<%cmd_1 : !hal.command_buffer> target(%_executable__split_reduction_pass2_dispatch_0 : !hal.executable)[0] workgroups([%c8, %c16, %c1])
      hal.return
    }
    hal.command_buffer.fill_buffer<%cmd_1 : !hal.command_buffer> target(%buffer_0 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_1 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_1 : !hal.command_buffer>
    %fence_2 = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence_2) commands([%cmd_1])
    %status_3 = hal.fence.await until([%fence_2]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status_3, "failed to wait on timepoint"
    %view = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c0, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    %view_4 = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c524288, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    check.expect_eq(%view, %view_4) : !hal.buffer_view
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::InlineDeviceSwitchesPass (iree-hal-inline-device-switches) ('func.func' operation: @_split_reduction_pass2) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  util.global private @_descriptor_set_layout_0 : !hal.descriptor_set_layout
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %descriptor_set_layout = hal.descriptor_set_layout.create device(%device : !hal.device) flags("None") bindings([#hal.descriptor_set.binding<0, storage_buffer, ReadOnly>, #hal.descriptor_set.binding<1, storage_buffer>]) : !hal.descriptor_set_layout
    util.global.store %descriptor_set_layout, @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    util.initializer.return
  }
  util.global private @_pipeline_layout_0 : !hal.pipeline_layout
  util.initializer {
    %_descriptor_set_layout_0 = util.global.load @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    %device = hal.ex.shared_device : !hal.device
    %pipeline_layout = hal.pipeline_layout.create device(%device : !hal.device) push_constants(0) layouts([%_descriptor_set_layout_0]) : !hal.pipeline_layout
    util.global.store %pipeline_layout, @_pipeline_layout_0 : !hal.pipeline_layout
    util.initializer.return
  }
  util.global private @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %ok, %value = hal.device.query<%device : !hal.device> key("hal.executable.format" :: "embedded-elf-x86_64") : i1, i1 = false
    cf.cond_br %value, ^bb1, ^bb2
  ^bb1:  // pred: ^bb0
    %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
    %exe = hal.executable.create device(%device : !hal.device) target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64) layouts([%_pipeline_layout_0]) : !hal.executable
    cf.br ^bb5(%exe : !hal.executable)
  ^bb2:  // pred: ^bb0
    %true = arith.constant true
    cf.cond_br %true, ^bb3, ^bb4
  ^bb3:  // pred: ^bb2
    %0 = util.null : !hal.executable
    cf.br ^bb5(%0 : !hal.executable)
  ^bb4:  // pred: ^bb2
    util.unreachable "device not supported in the compiled configuration"
  ^bb5(%1: !hal.executable):  // 2 preds: ^bb1, ^bb3
    util.global.store %1, @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    util.initializer.return
  }
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c268435488_i32 = arith.constant 268435488 : i32
    %c8 = arith.constant 8 : index
    %c16 = arith.constant 16 : index
    %c-1_i32 = arith.constant -1 : i32
    %c-1_i64 = arith.constant -1 : i64
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %cmd = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %status = hal.fence.await until([%fence]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %buffer_0 = hal.allocator.allocate<%allocator : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %cmd_1 = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    %ok, %value = hal.device.query<%device : !hal.device> key("hal.executable.format" :: "embedded-elf-x86_64") : i1, i1 = false
    cf.cond_br %value, ^bb1, ^bb2
  ^bb1:  // pred: ^bb0
    %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
    hal.command_buffer.push_descriptor_set<%cmd_1 : !hal.command_buffer> layout(%_pipeline_layout_0 : !hal.pipeline_layout)[%c0] bindings([
      %c0 = (%1 : !hal.buffer)[%c0, %len], 
      %c1 = (%buffer_0 : !hal.buffer)[%c0, %c1048576]
    ])
    %2 = hal.command_buffer.device<%cmd_1 : !hal.command_buffer> : !hal.device
    %_executable__split_reduction_pass2_dispatch_0 = util.global.load @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    hal.command_buffer.dispatch<%cmd_1 : !hal.command_buffer> target(%_executable__split_reduction_pass2_dispatch_0 : !hal.executable)[0] workgroups([%c8, %c16, %c1])
    cf.br ^bb3
  ^bb2:  // pred: ^bb0
    util.unreachable "device not supported in the compiled configuration"
  ^bb3:  // pred: ^bb1
    hal.command_buffer.fill_buffer<%cmd_1 : !hal.command_buffer> target(%buffer_0 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_1 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_1 : !hal.command_buffer>
    %fence_2 = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence_2) commands([%cmd_1])
    %status_3 = hal.fence.await until([%fence_2]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status_3, "failed to wait on timepoint"
    %view = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c0, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    %view_4 = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c524288, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    check.expect_eq(%view, %view_4) : !hal.buffer_view
    return
  }
}


// -----// IR Dump After mlir::iree_compiler::IREE::HAL::MemoizeDeviceQueriesPass (iree-hal-memoize-device-queries) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  util.global private @_device_query_0 : i1
  util.global private @_device_query_0_ok : i1
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %ok, %value = hal.device.query<%device : !hal.device> key("hal.executable.format" :: "embedded-elf-x86_64") : i1, i1 = false
    util.global.store %ok, @_device_query_0_ok : i1
    util.global.store %value, @_device_query_0 : i1
    util.initializer.return
  }
  util.global private @_descriptor_set_layout_0 : !hal.descriptor_set_layout
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %descriptor_set_layout = hal.descriptor_set_layout.create device(%device : !hal.device) flags("None") bindings([#hal.descriptor_set.binding<0, storage_buffer, ReadOnly>, #hal.descriptor_set.binding<1, storage_buffer>]) : !hal.descriptor_set_layout
    util.global.store %descriptor_set_layout, @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    util.initializer.return
  }
  util.global private @_pipeline_layout_0 : !hal.pipeline_layout
  util.initializer {
    %_descriptor_set_layout_0 = util.global.load @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    %device = hal.ex.shared_device : !hal.device
    %pipeline_layout = hal.pipeline_layout.create device(%device : !hal.device) push_constants(0) layouts([%_descriptor_set_layout_0]) : !hal.pipeline_layout
    util.global.store %pipeline_layout, @_pipeline_layout_0 : !hal.pipeline_layout
    util.initializer.return
  }
  util.global private @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %_device_query_0_ok = util.global.load @_device_query_0_ok : i1
    %_device_query_0 = util.global.load @_device_query_0 : i1
    cf.cond_br %_device_query_0, ^bb1, ^bb2
  ^bb1:  // pred: ^bb0
    %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
    %exe = hal.executable.create device(%device : !hal.device) target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64) layouts([%_pipeline_layout_0]) : !hal.executable
    cf.br ^bb5(%exe : !hal.executable)
  ^bb2:  // pred: ^bb0
    %true = arith.constant true
    cf.cond_br %true, ^bb3, ^bb4
  ^bb3:  // pred: ^bb2
    %0 = util.null : !hal.executable
    cf.br ^bb5(%0 : !hal.executable)
  ^bb4:  // pred: ^bb2
    util.unreachable "device not supported in the compiled configuration"
  ^bb5(%1: !hal.executable):  // 2 preds: ^bb1, ^bb3
    util.global.store %1, @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    util.initializer.return
  }
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c268435488_i32 = arith.constant 268435488 : i32
    %c8 = arith.constant 8 : index
    %c16 = arith.constant 16 : index
    %c-1_i32 = arith.constant -1 : i32
    %c-1_i64 = arith.constant -1 : i64
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %cmd = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %status = hal.fence.await until([%fence]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %buffer_0 = hal.allocator.allocate<%allocator : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %cmd_1 = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    %_device_query_0_ok = util.global.load @_device_query_0_ok : i1
    %_device_query_0 = util.global.load @_device_query_0 : i1
    cf.cond_br %_device_query_0, ^bb1, ^bb2
  ^bb1:  // pred: ^bb0
    %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
    hal.command_buffer.push_descriptor_set<%cmd_1 : !hal.command_buffer> layout(%_pipeline_layout_0 : !hal.pipeline_layout)[%c0] bindings([
      %c0 = (%1 : !hal.buffer)[%c0, %len], 
      %c1 = (%buffer_0 : !hal.buffer)[%c0, %c1048576]
    ])
    %2 = hal.command_buffer.device<%cmd_1 : !hal.command_buffer> : !hal.device
    %_executable__split_reduction_pass2_dispatch_0 = util.global.load @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    hal.command_buffer.dispatch<%cmd_1 : !hal.command_buffer> target(%_executable__split_reduction_pass2_dispatch_0 : !hal.executable)[0] workgroups([%c8, %c16, %c1])
    cf.br ^bb3
  ^bb2:  // pred: ^bb0
    util.unreachable "device not supported in the compiled configuration"
  ^bb3:  // pred: ^bb1
    hal.command_buffer.fill_buffer<%cmd_1 : !hal.command_buffer> target(%buffer_0 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_1 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_1 : !hal.command_buffer>
    %fence_2 = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence_2) commands([%cmd_1])
    %status_3 = hal.fence.await until([%fence_2]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status_3, "failed to wait on timepoint"
    %view = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c0, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    %view_4 = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c524288, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    check.expect_eq(%view, %view_4) : !hal.buffer_view
    return
  }
}


// -----// IR Dump After Canonicalizer (canonicalize) ('builtin.module' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  util.global private @_device_query_0 : i1
  util.global private @_device_query_0_ok : i1
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %ok, %value = hal.device.query<%device : !hal.device> key("hal.executable.format" :: "embedded-elf-x86_64") : i1, i1 = false
    util.global.store %ok, @_device_query_0_ok : i1
    util.global.store %value, @_device_query_0 : i1
    util.initializer.return
  }
  util.global private @_descriptor_set_layout_0 : !hal.descriptor_set_layout
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %descriptor_set_layout = hal.descriptor_set_layout.create device(%device : !hal.device) flags("None") bindings([#hal.descriptor_set.binding<0, storage_buffer, ReadOnly>, #hal.descriptor_set.binding<1, storage_buffer>]) : !hal.descriptor_set_layout
    util.global.store %descriptor_set_layout, @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    util.initializer.return
  }
  util.global private @_pipeline_layout_0 : !hal.pipeline_layout
  util.initializer {
    %_descriptor_set_layout_0 = util.global.load @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    %device = hal.ex.shared_device : !hal.device
    %pipeline_layout = hal.pipeline_layout.create device(%device : !hal.device) push_constants(0) layouts([%_descriptor_set_layout_0]) : !hal.pipeline_layout
    util.global.store %pipeline_layout, @_pipeline_layout_0 : !hal.pipeline_layout
    util.initializer.return
  }
  util.global private @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %_device_query_0 = util.global.load @_device_query_0 : i1
    cf.cond_br %_device_query_0, ^bb1, ^bb2
  ^bb1:  // pred: ^bb0
    %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
    %exe = hal.executable.create device(%device : !hal.device) target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64) layouts([%_pipeline_layout_0]) : !hal.executable
    cf.br ^bb3(%exe : !hal.executable)
  ^bb2:  // pred: ^bb0
    %0 = util.null : !hal.executable
    cf.br ^bb3(%0 : !hal.executable)
  ^bb3(%1: !hal.executable):  // 2 preds: ^bb1, ^bb2
    util.global.store %1, @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    util.initializer.return
  }
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c268435488_i32 = arith.constant 268435488 : i32
    %c8 = arith.constant 8 : index
    %c16 = arith.constant 16 : index
    %c-1_i32 = arith.constant -1 : i32
    %c-1_i64 = arith.constant -1 : i64
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %cmd = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %status = hal.fence.await until([%fence]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %buffer_0 = hal.allocator.allocate<%allocator : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %cmd_1 = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    %_device_query_0 = util.global.load @_device_query_0 : i1
    cf.cond_br %_device_query_0, ^bb1, ^bb2
  ^bb1:  // pred: ^bb0
    %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
    hal.command_buffer.push_descriptor_set<%cmd_1 : !hal.command_buffer> layout(%_pipeline_layout_0 : !hal.pipeline_layout)[%c0] bindings([
      %c0 = (%1 : !hal.buffer)[%c0, %len], 
      %c1 = (%buffer_0 : !hal.buffer)[%c0, %c1048576]
    ])
    %_executable__split_reduction_pass2_dispatch_0 = util.global.load @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    hal.command_buffer.dispatch<%cmd_1 : !hal.command_buffer> target(%_executable__split_reduction_pass2_dispatch_0 : !hal.executable)[0] workgroups([%c8, %c16, %c1])
    hal.command_buffer.fill_buffer<%cmd_1 : !hal.command_buffer> target(%buffer_0 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_1 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_1 : !hal.command_buffer>
    %fence_2 = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence_2) commands([%cmd_1])
    %status_3 = hal.fence.await until([%fence_2]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status_3, "failed to wait on timepoint"
    %view = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c0, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    %view_4 = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c524288, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    check.expect_eq(%view, %view_4) : !hal.buffer_view
    return
  ^bb2:  // pred: ^bb0
    util.unreachable "device not supported in the compiled configuration"
  }
}


// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) ('util.initializer' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  util.global private @_device_query_0 : i1
  util.global private @_device_query_0_ok : i1
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %ok, %value = hal.device.query<%device : !hal.device> key("hal.executable.format" :: "embedded-elf-x86_64") : i1, i1 = false
    util.global.store %value, @_device_query_0 : i1
    util.global.store %ok, @_device_query_0_ok : i1
    util.initializer.return
  }
  util.global private @_descriptor_set_layout_0 : !hal.descriptor_set_layout
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %descriptor_set_layout = hal.descriptor_set_layout.create device(%device : !hal.device) flags("None") bindings([#hal.descriptor_set.binding<0, storage_buffer, ReadOnly>, #hal.descriptor_set.binding<1, storage_buffer>]) : !hal.descriptor_set_layout
    util.global.store %descriptor_set_layout, @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    util.initializer.return
  }
  util.global private @_pipeline_layout_0 : !hal.pipeline_layout
  util.initializer {
    %_descriptor_set_layout_0 = util.global.load @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    %device = hal.ex.shared_device : !hal.device
    %pipeline_layout = hal.pipeline_layout.create device(%device : !hal.device) push_constants(0) layouts([%_descriptor_set_layout_0]) : !hal.pipeline_layout
    util.global.store %pipeline_layout, @_pipeline_layout_0 : !hal.pipeline_layout
    util.initializer.return
  }
  util.global private @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %_device_query_0 = util.global.load @_device_query_0 : i1
    cf.cond_br %_device_query_0, ^bb1, ^bb2
  ^bb1:  // pred: ^bb0
    %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
    %exe = hal.executable.create device(%device : !hal.device) target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64) layouts([%_pipeline_layout_0]) : !hal.executable
    cf.br ^bb3(%exe : !hal.executable)
  ^bb2:  // pred: ^bb0
    %0 = util.null : !hal.executable
    cf.br ^bb3(%0 : !hal.executable)
  ^bb3(%1: !hal.executable):  // 2 preds: ^bb1, ^bb2
    util.global.store %1, @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    util.initializer.return
  }
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 = llvm.add %252, %253  : i32
          %255 = llvm.insertelement %254, %250[%40 : i64] : vector<4xi32>
          %256 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %257 = llvm.extractelement %245[%13 : i64] : vector<4xi32>
          %258 = "llvm.intr.vector.reduce.add"(%256) : (vector<4xi32>) -> i32
          %259 = llvm.add %257, %258  : i32
          %260 = llvm.insertelement %259, %255[%36 : i64] : vector<4xi32>
          %261 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %262 = llvm.extractelement %245[%12 : i64] : vector<4xi32>
          %263 = "llvm.intr.vector.reduce.add"(%261) : (vector<4xi32>) -> i32
          %264 = llvm.add %262, %263  : i32
          %265 = llvm.insertelement %264, %260[%37 : i64] : vector<4xi32>
          llvm.store %265, %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %266 = llvm.add %77, %39  : i64
          llvm.br ^bb2(%266 : i64)
        ^bb7:  // pred: ^bb2
          %267 = llvm.add %75, %40  : i64
          llvm.br ^bb1(%267 : i64)
        ^bb8:  // pred: ^bb1
          llvm.return %0 : i32
        }
      }
    }
  }
  func.func private @_split_reduction_pass2() {
    %c268435488_i32 = arith.constant 268435488 : i32
    %c8 = arith.constant 8 : index
    %c16 = arith.constant 16 : index
    %c-1_i32 = arith.constant -1 : i32
    %c-1_i64 = arith.constant -1 : i64
    %c1048576 = arith.constant 1048576 : index
    %c0 = arith.constant 0 : index
    %c524288 = arith.constant 524288 : index
    %c67108864 = arith.constant 67108864 : index
    %c1_i32 = arith.constant 1 : i32
    %c128_i32 = arith.constant 128 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c1 = arith.constant 1 : index
    %device = hal.ex.shared_device : !hal.device
    %allocator = hal.device.allocator<%device : !hal.device> : !hal.allocator
    %buffer = hal.allocator.allocate<%allocator : !hal.allocator> type("DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage") : !hal.buffer{%c67108864}
    %cmd = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories(Transfer) : !hal.command_buffer
    hal.command_buffer.fill_buffer<%cmd : !hal.command_buffer> target(%buffer : !hal.buffer)[%c0, %c67108864] pattern(%c1_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd : !hal.command_buffer>
    %0 = util.null : !hal.fence
    %fence = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence) commands([%cmd])
    %status = hal.fence.await until([%fence]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status, "failed to wait on timepoint"
    %1 = util.do_not_optimize(%buffer) : !hal.buffer
    %len = hal.buffer.length<%1 : !hal.buffer> : index
    %buffer_0 = hal.allocator.allocate<%allocator : !hal.allocator> type("HostVisible|DeviceVisible|DeviceLocal") usage("TransferSource|TransferTarget|Transfer|DispatchStorageRead|DispatchStorageWrite|DispatchStorage|MappingScoped|MappingAccessRandom|Mapping") : !hal.buffer{%c1048576}
    %cmd_1 = hal.command_buffer.create device(%device : !hal.device) mode("OneShot|AllowInlineExecution") categories("Transfer|Dispatch") : !hal.command_buffer
    %_device_query_0 = util.global.load @_device_query_0 : i1
    cf.cond_br %_device_query_0, ^bb1, ^bb2
  ^bb1:  // pred: ^bb0
    %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
    hal.command_buffer.push_descriptor_set<%cmd_1 : !hal.command_buffer> layout(%_pipeline_layout_0 : !hal.pipeline_layout)[%c0] bindings([
      %c0 = (%1 : !hal.buffer)[%c0, %len], 
      %c1 = (%buffer_0 : !hal.buffer)[%c0, %c1048576]
    ])
    %_executable__split_reduction_pass2_dispatch_0 = util.global.load @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    hal.command_buffer.dispatch<%cmd_1 : !hal.command_buffer> target(%_executable__split_reduction_pass2_dispatch_0 : !hal.executable)[0] workgroups([%c8, %c16, %c1])
    hal.command_buffer.fill_buffer<%cmd_1 : !hal.command_buffer> target(%buffer_0 : !hal.buffer)[%c524288, %c524288] pattern(%c128_i32 : i32)
    hal.command_buffer.execution_barrier<%cmd_1 : !hal.command_buffer> source("Dispatch|Transfer|CommandRetire") target("CommandIssue|Dispatch|Transfer") flags("None")
    hal.command_buffer.finalize<%cmd_1 : !hal.command_buffer>
    %fence_2 = hal.fence.create device(%device : !hal.device) flags("None") : !hal.fence
    hal.device.queue.execute<%device : !hal.device> affinity(%c-1_i64) wait(%0) signal(%fence_2) commands([%cmd_1])
    %status_3 = hal.fence.await until([%fence_2]) timeout_millis(%c-1_i32) : i32
    util.status.check_ok %status_3, "failed to wait on timepoint"
    %view = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c0, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    %view_4 = hal.buffer_view.create buffer(%buffer_0 : !hal.buffer)[%c524288, %c524288] shape([%c512, %c256]) type(%c268435488_i32) encoding(%c1_i32) : !hal.buffer_view
    check.expect_eq(%view, %view_4) : !hal.buffer_view
    return
  ^bb2:  // pred: ^bb0
    util.unreachable "device not supported in the compiled configuration"
  }
}


// -----// IR Dump After SimplifyGlobalAccesses (iree-util-simplify-global-accesses) ('util.initializer' operation) //----- //
#device_target_llvm_cpu = #hal.device.target<"llvm-cpu", {executable_targets = [#hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>], legacy_sync}>
#executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu_features = "", data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", native_vector_size = 16 : index, target_triple = "x86_64-unknown-unknown-eabi-elf"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer>]>]>
#translation = #iree_codegen.translation_info<CPUDoubleTilingExpert>
module attributes {hal.device.targets = [#device_target_llvm_cpu]} {
  util.global private @_device_query_0 : i1
  util.global private @_device_query_0_ok : i1
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %ok, %value = hal.device.query<%device : !hal.device> key("hal.executable.format" :: "embedded-elf-x86_64") : i1, i1 = false
    util.global.store %value, @_device_query_0 : i1
    util.global.store %ok, @_device_query_0_ok : i1
    util.initializer.return
  }
  util.global private @_descriptor_set_layout_0 : !hal.descriptor_set_layout
  util.initializer {
    %device = hal.ex.shared_device : !hal.device
    %descriptor_set_layout = hal.descriptor_set_layout.create device(%device : !hal.device) flags("None") bindings([#hal.descriptor_set.binding<0, storage_buffer, ReadOnly>, #hal.descriptor_set.binding<1, storage_buffer>]) : !hal.descriptor_set_layout
    util.global.store %descriptor_set_layout, @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    util.initializer.return
  }
  util.global private @_pipeline_layout_0 : !hal.pipeline_layout
  util.initializer {
    %_descriptor_set_layout_0 = util.global.load @_descriptor_set_layout_0 : !hal.descriptor_set_layout
    %device = hal.ex.shared_device : !hal.device
    %pipeline_layout = hal.pipeline_layout.create device(%device : !hal.device) push_constants(0) layouts([%_descriptor_set_layout_0]) : !hal.pipeline_layout
    util.global.store %pipeline_layout, @_pipeline_layout_0 : !hal.pipeline_layout
    util.initializer.return
  }
  util.global private @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
  util.initializer {
    %_device_query_0 = util.global.load @_device_query_0 : i1
    %device = hal.ex.shared_device : !hal.device
    cf.cond_br %_device_query_0, ^bb1, ^bb2
  ^bb1:  // pred: ^bb0
    %_pipeline_layout_0 = util.global.load @_pipeline_layout_0 : !hal.pipeline_layout
    %exe = hal.executable.create device(%device : !hal.device) target(@_split_reduction_pass2_dispatch_0::@embedded_elf_x86_64) layouts([%_pipeline_layout_0]) : !hal.executable
    cf.br ^bb3(%exe : !hal.executable)
  ^bb2:  // pred: ^bb0
    %0 = util.null : !hal.executable
    cf.br ^bb3(%0 : !hal.executable)
  ^bb3(%1: !hal.executable):  // 2 preds: ^bb1, ^bb2
    util.global.store %1, @_executable__split_reduction_pass2_dispatch_0 : !hal.executable
    util.initializer.return
  }
  func.func @split_reduction_pass2() attributes {iree.abi.stub} {
    call @_split_reduction_pass2() : () -> ()
    return
  }
  hal.executable private @_split_reduction_pass2_dispatch_0 {
    hal.executable.variant public @embedded_elf_x86_64, target = #executable_target_embedded_elf_x86_64_ {
      hal.executable.export public @_split_reduction_pass2_dispatch_0_generic_512x256x128 ordinal(0) layout(#pipeline_layout) attributes {translation_info = #translation} {
      ^bb0(%arg0: !hal.device, %arg1: index, %arg2: index, %arg3: index):
        %c1 = arith.constant 1 : index
        %c16 = arith.constant 16 : index
        %c8 = arith.constant 8 : index
        hal.return %c8, %c16, %c1 : index, index, index
      }
      builtin.module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-unknown-eabi-elf"} {
        llvm.func internal @_split_reduction_pass2_dispatch_0_generic_512x256x128(%arg0: !llvm.ptr<struct<"iree_hal_executable_environment_v0_t", (ptr<i32>, ptr<func<i32 (ptr<func<i32 (ptr<i8>)>>, ptr<i8>)>>, ptr<ptr<func<i32 (ptr<i8>)>>>, struct<"iree_hal_processor_v0_t", (array<8 x i64>)>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg1: !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>> {llvm.align = 16 : i64, llvm.noalias}, %arg2: !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>> {llvm.align = 16 : i64, llvm.noalias}) -> i32 attributes {sym_visibility = "private"} {
          %0 = llvm.mlir.constant(0 : i32) : i32
          %1 = llvm.mlir.constant(15 : i64) : i64
          %2 = llvm.mlir.constant(14 : i64) : i64
          %3 = llvm.mlir.constant(13 : i64) : i64
          %4 = llvm.mlir.constant(12 : i64) : i64
          %5 = llvm.mlir.constant(11 : i64) : i64
          %6 = llvm.mlir.constant(10 : i64) : i64
          %7 = llvm.mlir.constant(9 : i64) : i64
          %8 = llvm.mlir.constant(8 : i64) : i64
          %9 = llvm.mlir.constant(7 : i64) : i64
          %10 = llvm.mlir.constant(6 : i64) : i64
          %11 = llvm.mlir.constant(5 : i64) : i64
          %12 = llvm.mlir.constant(3 : i64) : i64
          %13 = llvm.mlir.constant(2 : i64) : i64
          %14 = llvm.mlir.constant(4 : i64) : i64
          %15 = llvm.mlir.constant(32768 : i64) : i64
          %16 = llvm.mlir.constant(128 : i64) : i64
          %17 = llvm.mlir.constant(1 : i64) : i64
          %18 = llvm.mlir.constant(63 : index) : i64
          %19 = llvm.mlir.constant(128 : index) : i64
          %20 = llvm.mlir.constant(256 : index) : i64
          %21 = llvm.mlir.constant(32768 : index) : i64
          %22 = llvm.mlir.constant(0 : i64) : i64
          %23 = llvm.mlir.constant(dense<0> : vector<16xi32>) : vector<16xi32>
          %24 = llvm.mlir.constant(5 : index) : i64
          %25 = llvm.mlir.constant(6 : index) : i64
          %26 = llvm.mlir.constant(7 : index) : i64
          %27 = llvm.mlir.constant(8 : index) : i64
          %28 = llvm.mlir.constant(9 : index) : i64
          %29 = llvm.mlir.constant(10 : index) : i64
          %30 = llvm.mlir.constant(11 : index) : i64
          %31 = llvm.mlir.constant(12 : index) : i64
          %32 = llvm.mlir.constant(13 : index) : i64
          %33 = llvm.mlir.constant(14 : index) : i64
          %34 = llvm.mlir.constant(15 : index) : i64
          %35 = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
          %36 = llvm.mlir.constant(2 : index) : i64
          %37 = llvm.mlir.constant(3 : index) : i64
          %38 = llvm.mlir.constant(dense<0> : vector<1x4x4xi32>) : !llvm.array<1 x array<4 x vector<4xi32>>>
          %39 = llvm.mlir.constant(4 : index) : i64
          %40 = llvm.mlir.constant(1 : index) : i64
          %41 = llvm.mlir.constant(32 : index) : i64
          %42 = llvm.mlir.constant(0 : index) : i64
          %43 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %44 = llvm.extractvalue %43[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %45 = llvm.load %44 : !llvm.ptr<ptr<i8>>
          %46 = llvm.bitcast %45 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %47 = llvm.ptrtoint %46 : !llvm.ptr<i32> to i64
          %48 = llvm.and %47, %18  : i64
          %49 = llvm.icmp "eq" %48, %42 : i64
          "llvm.intr.assume"(%49) : (i1) -> ()
          %50 = llvm.load %arg1 : !llvm.ptr<struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)>>
          %51 = llvm.extractvalue %50[10] : !llvm.struct<"iree_hal_executable_dispatch_state_v0_t", (i32, i32, i16, i16, i32, i32, i16, i8, i8, ptr<i32>, ptr<ptr<i8>>, ptr<i64>)> 
          %52 = llvm.getelementptr %51[1] : (!llvm.ptr<ptr<i8>>) -> !llvm.ptr<ptr<i8>>
          %53 = llvm.load %52 : !llvm.ptr<ptr<i8>>
          %54 = llvm.bitcast %53 : !llvm.ptr<i8> to !llvm.ptr<i32>
          %55 = llvm.ptrtoint %54 : !llvm.ptr<i32> to i64
          %56 = llvm.and %55, %18  : i64
          %57 = llvm.icmp "eq" %56, %42 : i64
          "llvm.intr.assume"(%57) : (i1) -> ()
          %58 = llvm.load %arg2 : !llvm.ptr<struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)>>
          %59 = llvm.extractvalue %58[0] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %60 = llvm.zext %59 : i32 to i64
          %61 = llvm.extractvalue %58[1] : !llvm.struct<"iree_hal_executable_workgroup_state_v0_t", (i32, i32, i16, i16, i32, ptr<ptr<i8>>, i32)> 
          %62 = llvm.zext %61 : i32 to i64
          %63 = llvm.mul %62, %41  : i64
          %64 = llvm.mul %60, %41  : i64
          %65 = llvm.mul %63, %20  : i64
          %66 = llvm.add %65, %42  : i64
          %67 = llvm.mul %64, %40  : i64
          %68 = llvm.add %66, %67  : i64
          %69 = llvm.mul %63, %21  : i64
          %70 = llvm.add %69, %42  : i64
          %71 = llvm.mul %64, %19  : i64
          %72 = llvm.add %70, %71  : i64
          %73 = llvm.mul %22, %40  : i64
          %74 = llvm.add %72, %73  : i64
          llvm.br ^bb1(%42 : i64)
        ^bb1(%75: i64):  // 2 preds: ^bb0, ^bb7
          %76 = llvm.icmp "slt" %75, %41 : i64
          llvm.cond_br %76, ^bb2(%42 : i64), ^bb8
        ^bb2(%77: i64):  // 2 preds: ^bb1, ^bb6
          %78 = llvm.icmp "slt" %77, %41 : i64
          llvm.cond_br %78, ^bb3, ^bb7
        ^bb3:  // pred: ^bb2
          %79 = llvm.mul %75, %15  : i64
          %80 = llvm.add %74, %79  : i64
          %81 = llvm.mul %77, %16  : i64
          %82 = llvm.add %80, %81  : i64
          %83 = llvm.mul %22, %17  : i64
          %84 = llvm.add %82, %83  : i64
          llvm.br ^bb4(%42, %38 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb4(%85: i64, %86: !llvm.array<1 x array<4 x vector<4xi32>>>):  // 2 preds: ^bb3, ^bb5
          %87 = llvm.icmp "slt" %85, %41 : i64
          llvm.cond_br %87, ^bb5, ^bb6
        ^bb5:  // pred: ^bb4
          %88 = llvm.mul %42, %21  : i64
          %89 = llvm.add %84, %88  : i64
          %90 = llvm.mul %42, %19  : i64
          %91 = llvm.add %89, %90  : i64
          %92 = llvm.mul %85, %39  : i64
          %93 = llvm.add %91, %92  : i64
          %94 = llvm.add %93, %42  : i64
          %95 = llvm.getelementptr %46[%94] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %96 = llvm.bitcast %95 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %97 = llvm.load %96 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %98 = llvm.mul %40, %19  : i64
          %99 = llvm.add %89, %98  : i64
          %100 = llvm.add %99, %92  : i64
          %101 = llvm.add %100, %42  : i64
          %102 = llvm.getelementptr %46[%101] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %103 = llvm.bitcast %102 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %104 = llvm.load %103 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %105 = llvm.mul %36, %19  : i64
          %106 = llvm.add %89, %105  : i64
          %107 = llvm.add %106, %92  : i64
          %108 = llvm.add %107, %42  : i64
          %109 = llvm.getelementptr %46[%108] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %110 = llvm.bitcast %109 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %111 = llvm.load %110 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %112 = llvm.mul %37, %19  : i64
          %113 = llvm.add %89, %112  : i64
          %114 = llvm.add %113, %92  : i64
          %115 = llvm.add %114, %42  : i64
          %116 = llvm.getelementptr %46[%115] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %117 = llvm.bitcast %116 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %118 = llvm.load %117 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %119 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %120 = llvm.extractelement %119[%22 : i64] : vector<4xi32>
          %121 = llvm.extractelement %97[%22 : i64] : vector<4xi32>
          %122 = llvm.add %121, %120  : i32
          %123 = llvm.insertelement %122, %23[%42 : i64] : vector<16xi32>
          %124 = llvm.extractelement %119[%17 : i64] : vector<4xi32>
          %125 = llvm.extractelement %97[%17 : i64] : vector<4xi32>
          %126 = llvm.add %125, %124  : i32
          %127 = llvm.insertelement %126, %123[%40 : i64] : vector<16xi32>
          %128 = llvm.extractelement %119[%13 : i64] : vector<4xi32>
          %129 = llvm.extractelement %97[%13 : i64] : vector<4xi32>
          %130 = llvm.add %129, %128  : i32
          %131 = llvm.insertelement %130, %127[%36 : i64] : vector<16xi32>
          %132 = llvm.extractelement %119[%12 : i64] : vector<4xi32>
          %133 = llvm.extractelement %97[%12 : i64] : vector<4xi32>
          %134 = llvm.add %133, %132  : i32
          %135 = llvm.insertelement %134, %131[%37 : i64] : vector<16xi32>
          %136 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %137 = llvm.extractelement %136[%22 : i64] : vector<4xi32>
          %138 = llvm.extractelement %104[%22 : i64] : vector<4xi32>
          %139 = llvm.add %138, %137  : i32
          %140 = llvm.insertelement %139, %135[%39 : i64] : vector<16xi32>
          %141 = llvm.extractelement %136[%17 : i64] : vector<4xi32>
          %142 = llvm.extractelement %104[%17 : i64] : vector<4xi32>
          %143 = llvm.add %142, %141  : i32
          %144 = llvm.insertelement %143, %140[%24 : i64] : vector<16xi32>
          %145 = llvm.extractelement %136[%13 : i64] : vector<4xi32>
          %146 = llvm.extractelement %104[%13 : i64] : vector<4xi32>
          %147 = llvm.add %146, %145  : i32
          %148 = llvm.insertelement %147, %144[%25 : i64] : vector<16xi32>
          %149 = llvm.extractelement %136[%12 : i64] : vector<4xi32>
          %150 = llvm.extractelement %104[%12 : i64] : vector<4xi32>
          %151 = llvm.add %150, %149  : i32
          %152 = llvm.insertelement %151, %148[%26 : i64] : vector<16xi32>
          %153 = llvm.extractvalue %86[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %154 = llvm.extractelement %153[%22 : i64] : vector<4xi32>
          %155 = llvm.extractelement %111[%22 : i64] : vector<4xi32>
          %156 = llvm.add %155, %154  : i32
          %157 = llvm.insertelement %156, %152[%27 : i64] : vector<16xi32>
          %158 = llvm.extractelement %153[%17 : i64] : vector<4xi32>
          %159 = llvm.extractelement %111[%17 : i64] : vector<4xi32>
          %160 = llvm.add %159, %158  : i32
          %161 = llvm.insertelement %160, %157[%28 : i64] : vector<16xi32>
          %162 = llvm.extractelement %153[%13 : i64] : vector<4xi32>
          %163 = llvm.extractelement %111[%13 : i64] : vector<4xi32>
          %164 = llvm.add %163, %162  : i32
          %165 = llvm.insertelement %164, %161[%29 : i64] : vector<16xi32>
          %166 = llvm.extractelement %153[%12 : i64] : vector<4xi32>
          %167 = llvm.extractelement %111[%12 : i64] : vector<4xi32>
          %168 = llvm.add %167, %166  : i32
          %169 = llvm.insertelement %168, %165[%30 : i64] : vector<16xi32>
          %170 = llvm.extractvalue %86[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %171 = llvm.extractelement %170[%22 : i64] : vector<4xi32>
          %172 = llvm.extractelement %118[%22 : i64] : vector<4xi32>
          %173 = llvm.add %172, %171  : i32
          %174 = llvm.insertelement %173, %169[%31 : i64] : vector<16xi32>
          %175 = llvm.extractelement %170[%17 : i64] : vector<4xi32>
          %176 = llvm.extractelement %118[%17 : i64] : vector<4xi32>
          %177 = llvm.add %176, %175  : i32
          %178 = llvm.insertelement %177, %174[%32 : i64] : vector<16xi32>
          %179 = llvm.extractelement %170[%13 : i64] : vector<4xi32>
          %180 = llvm.extractelement %118[%13 : i64] : vector<4xi32>
          %181 = llvm.add %180, %179  : i32
          %182 = llvm.insertelement %181, %178[%33 : i64] : vector<16xi32>
          %183 = llvm.extractelement %170[%12 : i64] : vector<4xi32>
          %184 = llvm.extractelement %118[%12 : i64] : vector<4xi32>
          %185 = llvm.add %184, %183  : i32
          %186 = llvm.insertelement %185, %182[%34 : i64] : vector<16xi32>
          %187 = llvm.extractelement %186[%22 : i64] : vector<16xi32>
          %188 = llvm.extractvalue %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %189 = llvm.insertelement %187, %188[%22 : i64] : vector<4xi32>
          %190 = llvm.insertvalue %189, %38[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %191 = llvm.extractelement %186[%17 : i64] : vector<16xi32>
          %192 = llvm.insertelement %191, %189[%17 : i64] : vector<4xi32>
          %193 = llvm.insertvalue %192, %190[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %194 = llvm.extractelement %186[%13 : i64] : vector<16xi32>
          %195 = llvm.insertelement %194, %192[%13 : i64] : vector<4xi32>
          %196 = llvm.insertvalue %195, %193[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %197 = llvm.extractelement %186[%12 : i64] : vector<16xi32>
          %198 = llvm.insertelement %197, %195[%12 : i64] : vector<4xi32>
          %199 = llvm.insertvalue %198, %196[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %200 = llvm.extractelement %186[%14 : i64] : vector<16xi32>
          %201 = llvm.extractvalue %38[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %202 = llvm.insertelement %200, %201[%22 : i64] : vector<4xi32>
          %203 = llvm.insertvalue %202, %199[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %204 = llvm.extractelement %186[%11 : i64] : vector<16xi32>
          %205 = llvm.insertelement %204, %202[%17 : i64] : vector<4xi32>
          %206 = llvm.insertvalue %205, %203[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %207 = llvm.extractelement %186[%10 : i64] : vector<16xi32>
          %208 = llvm.insertelement %207, %205[%13 : i64] : vector<4xi32>
          %209 = llvm.insertvalue %208, %206[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %210 = llvm.extractelement %186[%9 : i64] : vector<16xi32>
          %211 = llvm.insertelement %210, %208[%12 : i64] : vector<4xi32>
          %212 = llvm.insertvalue %211, %209[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %213 = llvm.extractelement %186[%8 : i64] : vector<16xi32>
          %214 = llvm.extractvalue %38[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %215 = llvm.insertelement %213, %214[%22 : i64] : vector<4xi32>
          %216 = llvm.insertvalue %215, %212[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %217 = llvm.extractelement %186[%7 : i64] : vector<16xi32>
          %218 = llvm.insertelement %217, %215[%17 : i64] : vector<4xi32>
          %219 = llvm.insertvalue %218, %216[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %220 = llvm.extractelement %186[%6 : i64] : vector<16xi32>
          %221 = llvm.insertelement %220, %218[%13 : i64] : vector<4xi32>
          %222 = llvm.insertvalue %221, %219[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %223 = llvm.extractelement %186[%5 : i64] : vector<16xi32>
          %224 = llvm.insertelement %223, %221[%12 : i64] : vector<4xi32>
          %225 = llvm.insertvalue %224, %222[0, 2] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %226 = llvm.extractelement %186[%4 : i64] : vector<16xi32>
          %227 = llvm.extractvalue %38[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %228 = llvm.insertelement %226, %227[%22 : i64] : vector<4xi32>
          %229 = llvm.insertvalue %228, %225[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %230 = llvm.extractelement %186[%3 : i64] : vector<16xi32>
          %231 = llvm.insertelement %230, %228[%17 : i64] : vector<4xi32>
          %232 = llvm.insertvalue %231, %229[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %233 = llvm.extractelement %186[%2 : i64] : vector<16xi32>
          %234 = llvm.insertelement %233, %231[%13 : i64] : vector<4xi32>
          %235 = llvm.insertvalue %234, %232[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %236 = llvm.extractelement %186[%1 : i64] : vector<16xi32>
          %237 = llvm.insertelement %236, %234[%12 : i64] : vector<4xi32>
          %238 = llvm.insertvalue %237, %235[0, 3] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %239 = llvm.add %85, %40  : i64
          llvm.br ^bb4(%239, %238 : i64, !llvm.array<1 x array<4 x vector<4xi32>>>)
        ^bb6:  // pred: ^bb4
          %240 = llvm.mul %75, %20  : i64
          %241 = llvm.add %68, %240  : i64
          %242 = llvm.add %241, %77  : i64
          %243 = llvm.getelementptr %54[%242] : (!llvm.ptr<i32>, i64) -> !llvm.ptr<i32>
          %244 = llvm.bitcast %243 : !llvm.ptr<i32> to !llvm.ptr<vector<4xi32>>
          %245 = llvm.load %244 {alignment = 4 : i64} : !llvm.ptr<vector<4xi32>>
          %246 = llvm.extractvalue %86[0, 0] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %247 = llvm.extractelement %245[%22 : i64] : vector<4xi32>
          %248 = "llvm.intr.vector.reduce.add"(%246) : (vector<4xi32>) -> i32
          %249 = llvm.add %247, %248  : i32
          %250 = llvm.insertelement %249, %35[%42 : i64] : vector<4xi32>
          %251 = llvm.extractvalue %86[0, 1] : !llvm.array<1 x array<4 x vector<4xi32>>> 
          %252 = llvm.extractelement %245[%17 : i64] : vector<4xi32>
          %253 = "llvm.intr.vector.reduce.add"(%251) : (vector<4xi32>) -> i32
          %254 =