Created
November 6, 2023 00:57
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arm64_msr.py
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import struct | |
Op0_shift = 19 | |
Op1_shift = 16 | |
CRn_shift = 12 | |
CRm_shift = 8 | |
Op2_shift = 5 | |
MAX_OP0 = 3 | |
MAX_OP1 = 7 | |
MAX_OP2 = 7 | |
MAX_CN = 15 | |
MAX_CM = 15 | |
MAX_REG = 31 | |
def sys_reg(op0, op1, cn, cm, op2): | |
assert ((op0 <= MAX_OP0) and (op1 <= MAX_OP1) and (op2 <= MAX_OP2) | |
and (cn <= MAX_CN) and (cm <= MAX_CM)) | |
return (((op0) << Op0_shift) | ((op1) << Op1_shift) | | |
((cn) << CRn_shift) | ((cm) << CRm_shift) | | |
((op2) << Op2_shift)) | |
def msr_insn(sysreg: int, reg: int): | |
assert (reg <= 31 and reg >= 0) | |
return (0xd5000000 | sysreg | reg) | |
def mrs_insn(reg: int, sysreg: int): | |
assert (reg <= 31 and reg >= 0) | |
return (0xd5200000 | sysreg | reg) | |
if __name == '__main__': | |
print(struct.pack("<L", msr_insn(sys_reg(0, 1, 1, 1, 1), 1)).hex()) | |
print(struct.pack("<L", mrs_insn(1, sys_reg(0, 1, 1, 1, 1))).hex()) |
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