wayne1029jihad

module LFSR (CLK, RESET_n, out);
input CLK, RESET_n;
output wire out;


always @(`CLK)begin
	if(RESET)
		dff[4:0] <= 5'b00001;
	else
		dff[4:0] <= {exdff[3:0],exdff[1] ^ exdff[4]};