Basic shift register in Verilog that targets a tinyFPGA-B2 pcf. Note: this is just for learning, don't do it this way.

top.v

// shift_register - top.v
//
// Description:
// shifts bits to left
// Pins are defined in pins.pcf file.
//

// out <-- pin13, pin12, pin11, pin10...,pin6  <-- pin5 in

module top (
   output pin1_usb_dp,// USB pull-up enable, set low to disable
   output pin2_usb_dn,
   input  pin3_clk_16mhz,   // 16 MHz on-board clock
   output pin13,   // out bit
   output pin12,
   output pin11,
   output pin10,
   output pin9,
   output pin8,
   output pin7,
   output pin6,   // in bit
   input  pin5    // 1 bit data in
   );

   reg [22:0] clk_1hz_counter = 23'b0;  // 1 Hz clock generation counter
   reg        clk_1hz = 1'b0;           // 1 Hz clock

   reg bit0;
   reg bit1;
   reg bit2;
   reg bit3;
   reg bit4;
   reg bit5;
   reg bit6;
   reg bit7;

   // 2 Hz clock
   always @(posedge pin3_clk_16mhz) begin
      if (clk_1hz_counter < 23'd7_999_999)
         clk_1hz_counter <= clk_1hz_counter + 23'd4;
      else begin
         clk_1hz_counter <= 23'b0;
         clk_1hz <= ~clk_1hz;
      end
   end

   always @(posedge clk_1hz) begin
      bit7 <= bit6;
      bit6 <= bit5;
      bit5 <= bit4;
      bit4 <= bit3;
      bit3 <= bit2;
      bit2 <= bit1;
      bit1 <= bit0;
      bit0 <= pin5;  // <-- input
   end

   assign pin13 = bit7;
   assign pin12 = bit6;
   assign pin11 = bit5;
   assign pin10 = bit4;
   assign pin9 = bit3;
   assign pin8 = bit2;
   assign pin7 = bit1;
   assign pin6 = bit0;

   assign pin1_usb_dp = 1'b0;
   assign pin2_usb_dn = 1'b0;

endmodule  // top

Shift register pulsed by a button: