Verilog cylon using Icestorm framework and targeting the tinyFPGA-B2 board

top.v

// cylon effect - top.v
//
// pins are relative to the tinyFPGA-B2
// I really need to stop using reg bits and use a vector. <-- lazy person.

module top (
   output pin1_usb_dp,// USB pull-up enable, set low to disable
   output pin2_usb_dn,
   input  pin3_clk_16mhz,   // 16 MHz on-board clock
   output pin13,
   output pin12,
   output pin11,
   output pin10,
   output pin9,
   output pin8,
   output pin7,
   output pin6,
   output pin5,
   output pin4
   );

   reg [22:0] clk_1hz_counter = 23'b0;  // 1 Hz clock generation counter
   reg        clk_1hz = 1'b0;           // 1 Hz clock

   reg bit0;
   reg bit1;
   reg bit2;
   reg bit3;
   reg bit4;
   reg bit5;
   reg bit6;
   reg bit7;
   reg bit8;
   reg bit9;

   reg direction = 0;  // Initial direction is from pin4 to pin13
   reg[3:0] counter;

   // 16 Hz clock
   always @(posedge pin3_clk_16mhz) begin
      if (clk_1hz_counter < 23'd7_999_999)
         clk_1hz_counter <= clk_1hz_counter + 23'd16;
      else begin
         clk_1hz_counter <= 23'b0;
         clk_1hz <= ~clk_1hz;
      end
   end

   initial begin
      bit0 = 1;
      counter = 0;
   end

   always @(posedge clk_1hz) begin
      if (counter == 9) begin
         direction = ~direction;
         counter = 0;
      end

      if (direction == 0) begin
         bit9 <= bit8;
         bit8 <= bit7;
         bit7 <= bit6;
         bit6 <= bit5;
         bit5 <= bit4;
         bit4 <= bit3;
         bit3 <= bit2;
         bit2 <= bit1;
         bit1 <= bit0;
         bit0 <= 0;
      end
      else begin
         bit9 <= 0;
         bit8 <= bit9;
         bit7 <= bit8;
         bit6 <= bit7;
         bit5 <= bit6;
         bit4 <= bit5;
         bit3 <= bit4;
         bit2 <= bit3;
         bit1 <= bit2;
         bit0 <= bit1;
      end

      counter <= #1 counter + 1;
   end

   assign pin13 = bit9;
   assign pin12 = bit8;
   assign pin11 = bit7;
   assign pin10 = bit6;
   assign pin9  = bit5;
   assign pin8  = bit4;
   assign pin7  = bit3;
   assign pin6  = bit2;
   assign pin5  = bit1;
   assign pin4  = bit0;

   assign pin1_usb_dp = 1'b0;
   assign pin2_usb_dn = 1'b0;

endmodule  // top