See https://github.com/YosysHQ/yosys/pull/1406

chargen.pcf

# iCE40HX8K-B-EVN
set_io clk J3
set_io tx  B12

chargen.v

module uart_tx(...);
  parameter CLK_FREQ = 12_000_000;
  parameter BIT_RATE = 115200;

  input clk;
  output tx;
  input [7:0] data;
  input stb;
  output ack;

  reg busy = 0;
  reg [31:0] divisor = 0;
  reg [8:0] shreg = 8'h1ff;
  reg [3:0] bitno = 4'd0;

  assign tx = shreg[0];

  always @(posedge clk) begin
    if (!busy || divisor == 0)
      divisor <= CLK_FREQ / BIT_RATE;
    else
      divisor <= divisor - 1;
  end

  always @(posedge clk) begin
    if (!busy && stb) begin
      shreg <= {data, 1'b0};
      bitno <= 4'd0;
      busy <= 1'b1;
    end else if (busy && divisor == 0) begin
      shreg <= {1'b1, shreg[8:1]};
      bitno <= bitno + 4'd1;
      busy <= (bitno != 4'd9);
    end
  end

  assign ack = ~busy;
endmodule

module top(...);
  input clk;
  output tx;

  reg [7:0] gen_data = "A";
  wire gen_next;
  always @(posedge clk) begin
    if (gen_next)
      if (gen_data == "Z")
        gen_data <= "A";
      else
        gen_data <= gen_data + 8'd1;
  end

  wire [7:0] uart_data;
  wire uart_stb;
  wire uart_ack;

  \nmigen.lib.fifo.SyncFIFOBuffered #(
    .depth(256),
    .width(8),
  ) fifo (
    .clk(clk),
    .rst(1'b0),
    .w_data(gen_data),
    .w_rdy(gen_next),
    .w_en(1'b1),
    .r_data(uart_data),
    .r_rdy(uart_stb),
    .r_en(uart_ack),
  );

  uart_tx uart_tx (
    .clk(clk),
    .tx(tx),
    .data(uart_data),
    .stb(uart_stb),
    .ack(uart_ack),
  );
endmodule

chargen.ys

connect_rpc -exec nmigen-rpc yosys nmigen.lib.fifo.*
read_verilog chargen.v
synth_ice40 -top top -json chargen.json

chargen_sim.v

`timescale 1ns/1ps
`include "chargen_sim.gen.v"
module bench();
  reg clk;
  wire tx;

  top top (.clk(clk), .tx(tx));

  initial begin
    $dumpfile("chargen_sim.vcd");
    $dumpvars();
    #1000000
    $finish();
  end

  always begin
    #83; clk = 1;
    #83; clk = 0;
  end
endmodule

chargen_sim.ys

connect_rpc -exec nmigen-rpc yosys nmigen.lib.fifo.*
read_verilog chargen.v
hierarchy -top top
# the following step is required to post-process nMigen RTLIL output such
# that it can be read by iverilog
synth -run coarse -noalumacc -nofsm
write_verilog chargen_sim.gen.v

simulate.sh

#!/bin/sh
yosys chargen_sim.ys
iverilog chargen_sim.v -o chargen_sim
./chargen_sim

synthesize.sh

#!/bin/sh -e
yosys chargen.ys
nextpnr-ice40 --hx8k --package ct256 --json chargen.json --pcf chargen.pcf --asc chargen.asc
icepack chargen.asc chargen.bin