iCE40HX8K-B-EVM Yosys example

blink.v

module LedBlink (
    input clk_12mhz,
    output [7:0] leds
  );
  
  reg [23:0] counter;
  always @(posedge clk_12mhz)
    counter <= counter - 1;
   
  assign leds = { counter[23], 7'b0 };

endmodule

build.sh

#!/bin/sh -ex
yosys -p "read_verilog -noautowire blink.v" -p "synth_ice40 -blif blink.blif"
arachne-pnr -d 8k -p iCE40HX8K-B-EVM.pcf -P ct256 blink.blif -o blink.txt
icetime -d hx8k -p iCE40HX8K-B-EVM.pcf -P ct256 blink.txt
icepack blink.txt blink.bin
iceprog -S blink.bin

iCE40HX8K-B-EVM.pcf

set_io clk_12mhz  J3

# D9
set_io --warn-no-port leds[0]    B5
# D8
set_io --warn-no-port leds[1]    B4
# D7
set_io --warn-no-port leds[2]    A2
# D6
set_io --warn-no-port leds[3]    A1
# D5
set_io --warn-no-port leds[4]    C5
# D4
set_io --warn-no-port leds[5]    C4
# D3
set_io --warn-no-port leds[6]    B3
# D2
set_io --warn-no-port leds[7]    C3

set_io --warn-no-port uart_tx    B12
set_io --warn-no-port uart_rx    B10

set_io --warn-no-port debug1     B16
set_io --warn-no-port debug2     C16
set_io --warn-no-port debug3     D16
set_io --warn-no-port debug4     E16