Created
December 19, 2015 01:50
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st8 device tree decompilation after it was compiled in tree of linux-next
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| /dts-v1/; | |
| / { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| compatible = "nvidia,st8", "nvidia,tegra124"; | |
| interrupt-parent = <0x1>; | |
| model = "NVIDIA SHIELD Tablet"; | |
| host1x@50000000 { | |
| compatible = "nvidia,tegra124-host1x", "simple-bus"; | |
| reg = <0x0 0x50000000 0x0 0x34000>; | |
| interrupts = <0x0 0x41 0x4 0x0 0x43 0x4>; | |
| clocks = <0x2 0x1c>; | |
| resets = <0x2 0x1c>; | |
| reset-names = "host1x"; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x1000000>; | |
| dsi { | |
| panel-a-wuxga-8-0 { | |
| status = "okay"; | |
| compatible = "a,wuxga-8-0"; | |
| nvidia,dsi-instance = <0x0>; | |
| nvidia,dsi-n-data-lanes = <0x4>; | |
| nvidia,dsi-pixel-format = <0x3>; | |
| nvidia,dsi-refresh-rate = <0x3c>; | |
| nvidia,dsi-video-data-type = <0x0>; | |
| nvidia,dsi-video-clock-mode = <0x1>; | |
| nvidia,dsi-video-burst-mode = <0x0>; | |
| nvidia,dsi-virtual-channel = <0x0>; | |
| nvidia,dsi-panel-reset = <0x1>; | |
| nvidia,dsi-power-saving-suspend = <0x1>; | |
| nvidia,dsi-ulpm-not-support = <0x1>; | |
| nvidia,dsi-dpd-pads = <0x4 0x8>; | |
| nvidia,dsi-boardinfo = <0x6e1 0x0 0x0 0x1>; | |
| nvidia,panel-rst-gpio = <0x3 0x6c 0x0>; | |
| nvidia,panel-bl-pwm-gpio = <0x3 0x39 0x0>; | |
| disp-default-out { | |
| nvidia,out-type = <0x2>; | |
| nvidia,out-width = <0x6b>; | |
| nvidia,out-height = <0xac>; | |
| nvidia,out-flags = <0x0>; | |
| nvidia,out-parent-clk = "pll_d_out0"; | |
| nvidia,out-xres = <0x4b0>; | |
| nvidia,out-yres = <0x780>; | |
| nvidia,out-rotation = <0xb4>; | |
| }; | |
| display-timings { | |
| 1200x1920-32 { | |
| clock-frequency = <0x948edc0>; | |
| hactive = <0x4b0>; | |
| vactive = <0x780>; | |
| hfront-porch = <0x40>; | |
| hback-porch = <0x36>; | |
| hsync-len = <0xa>; | |
| vfront-porch = <0x3>; | |
| vback-porch = <0x1e>; | |
| vsync-len = <0x2>; | |
| nvidia,h-ref-to-sync = <0x4>; | |
| nvidia,v-ref-to-sync = <0x1>; | |
| }; | |
| }; | |
| smartdimmer { | |
| status = "okay"; | |
| nvidia,turn-off-brightness = <0x32>; | |
| nvidia,turn-on-brightness = <0x4b>; | |
| nvidia,use-auto-pwm = <0x0>; | |
| nvidia,hw-update-delay = <0x0>; | |
| nvidia,bin-width = <0xffffffff>; | |
| nvidia,aggressiveness = <0x5>; | |
| nvidia,use-vid-luma = <0x0>; | |
| nvidia,phase-in-settings = <0x0>; | |
| nvidia,phase-in-adjustments = <0x0>; | |
| nvidia,k-limit-enable = <0x1>; | |
| nvidia,k-limit = <0xc8>; | |
| nvidia,sd-window-enable = <0x0>; | |
| nvidia,soft-clipping-enable = <0x1>; | |
| nvidia,soft-clipping-threshold = <0x80>; | |
| nvidia,smooth-k-enable = <0x1>; | |
| nvidia,smooth-k-incr = <0x4>; | |
| nvidia,coeff = <0x5 0x9 0x2>; | |
| nvidia,fc = <0x0 0x0>; | |
| nvidia,blp = <0x400 0xff>; | |
| nvidia,bltf = <0x39 0x41 0x49 0x52 0x5c 0x67 0x72 0x7d 0x8a 0x96 0xa4 0xb2 0xc1 0xd0 0xe0 0xf1>; | |
| nvidia,lut = <0xff 0xff 0xff 0xc7 0xc7 0xc7 0x99 0x99 0x99 0x74 0x74 0x74 0x55 0x55 0x55 0x3b 0x3b 0x3b 0x24 0x24 0x24 0x11 0x11 0x11 0x0 0x0 0x0>; | |
| nvidia,use-vpulse2 = <0x1>; | |
| nvidia,bl-device-name = "pwm-backlight"; | |
| }; | |
| cmu { | |
| nvidia,cmu-csc = <0xf7 0x3f2 0x16 0x3f4 0x101 0x3e2 0x3ff 0x3ff 0xde>; | |
| nvidia,cmu-lut2 = <0x0 0x1 0x3 0x4 0x6 0x7 0x8 0x9 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x13 0x14 0x15 0x16 0x16 0x17 0x17 0x18 0x19 0x19 0x1a 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1c 0x1d 0x1d 0x1d 0x1e 0x1e 0x1e 0x1f 0x1f 0x1f 0x1f 0x20 0x20 0x20 0x21 0x21 0x21 0x21 0x22 0x22 0x22 0x23 0x23 0x23 0x23 0x24 0x24 0x24 0x25 0x25 0x25 0x25 0x26 0x26 0x26 0x26 0x27 0x27 0x27 0x28 0x28 0x28 0x28 0x29 0x29 0x29 0x2a 0x2a 0x2a 0x2a 0x2b 0x2b 0x2b 0x2b 0x2c 0x2c 0x2c 0x2c 0x2d 0x2d 0x2d 0x2d 0x2e 0x2e 0x2e 0x2e 0x2f 0x2f 0x2f 0x2f 0x30 0x30 0x30 0x30 0x31 0x31 0x31 0x31 0x32 0x32 0x32 0x32 0x32 0x33 0x33 0x33 0x33 0x34 0x34 0x34 0x34 0x34 0x35 0x35 0x35 0x35 0x35 0x36 0x36 0x36 0x36 0x36 0x37 0x37 0x37 0x37 0x37 0x37 0x38 0x38 0x38 0x38 0x38 0x39 0x39 0x39 0x39 0x39 0x39 0x3a 0x3a 0x3a 0x3a 0x3a 0x3a 0x3b 0x3b 0x3b 0x3b 0x3b 0x3b 0x3c 0x3c 0x3c 0x3c 0x3c 0x3c 0x3d 0x3d 0x3d 0x3d 0x3d 0x3d 0x3e 0x3e 0x3e 0x3e 0x3e 0x3e 0x3f 0x3f 0x3f 0x3f 0x3f 0x3f 0x3f 0x40 0x40 0x40 0x40 0x40 0x40 0x41 0x41 0x41 0x41 0x41 0x41 0x41 0x42 0x42 0x42 0x42 0x42 0x42 0x43 0x43 0x43 0x43 0x43 0x43 0x43 0x44 0x44 0x44 0x44 0x44 0x44 0x44 0x45 0x45 0x45 0x45 0x45 0x45 0x46 0x46 0x46 0x46 0x46 0x46 0x46 0x47 0x47 0x47 0x47 0x47 0x47 0x47 0x48 0x48 0x48 0x48 0x48 0x48 0x48 0x49 0x49 0x49 0x49 0x49 0x49 0x49 0x4a 0x4a 0x4a 0x4a 0x4a 0x4a 0x4a 0x4a 0x4b 0x4b 0x4b 0x4b 0x4b 0x4b 0x4b 0x4c 0x4c 0x4c 0x4c 0x4c 0x4c 0x4c 0x4d 0x4d 0x4d 0x4d 0x4d 0x4d 0x4d 0x4d 0x4e 0x4e 0x4e 0x4e 0x4e 0x4e 0x4e 0x4e 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f 0x4f 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x50 0x51 0x51 0x51 0x51 0x51 0x51 0x51 0x51 0x51 0x52 0x52 0x52 0x52 0x52 0x52 0x52 0x52 0x52 0x53 0x53 0x53 0x53 0x53 0x53 0x53 0x53 0x53 0x54 0x54 0x54 0x54 0x54 0x54 0x54 0x54 0x54 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x56 0x56 0x56 0x56 0x56 0x56 0x56 0x56 0x56 0x56 0x57 0x57 0x57 0x57 0x57 0x57 0x57 0x57 0x57 0x57 0x58 0x58 0x58 0x58 0x58 0x58 0x58 0x58 0x58 0x58 0x58 0x59 0x59 0x59 0x59 0x59 0x59 0x59 0x59 0x59 0x59 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5b 0x5b 0x5b 0x5b 0x5b 0x5b 0x5b 0x5b 0x5b 0x5b 0x5b 0x5c 0x5c 0x5c 0x5c 0x5c 0x5c 0x5c 0x5c 0x5c 0x5c 0x5c 0x5d 0x5d 0x5d 0x5d 0x5d 0x5d 0x5d 0x5d 0x5d 0x5d 0x5d 0x5d 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x5f 0x5f 0x5f 0x5f 0x5f 0x5f 0x5f 0x5f 0x5f 0x5f 0x5f 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x61 0x61 0x61 0x61 0x61 0x61 0x61 0x61 0x61 0x61 0x61 0x61 0x62 0x62 0x62 0x62 0x62 0x62 0x62 0x62 0x62 0x62 0x62 0x63 0x63 0x63 0x63 0x63 0x63 0x63 0x63 0x63 0x63 0x63 0x64 0x64 0x64 0x64 0x65 0x66 0x67 0x67 0x68 0x69 0x69 0x6a 0x6b 0x6c 0x6c 0x6d 0x6e 0x6e 0x6f 0x70 0x70 0x71 0x72 0x72 0x73 0x73 0x74 0x75 0x75 0x76 0x77 0x77 0x78 0x78 0x79 0x79 0x7a 0x7b 0x7b 0x7c 0x7c 0x7d 0x7d 0x7e 0x7e 0x7f 0x7f 0x80 0x80 0x81 0x81 0x82 0x82 0x83 0x83 0x84 0x84 0x85 0x85 0x86 0x86 0x87 0x87 0x88 0x88 0x89 0x89 0x89 0x8a 0x8a 0x8b 0x8b 0x8c 0x8c 0x8d 0x8d 0x8e 0x8e 0x8e 0x8f 0x8f 0x90 0x90 0x91 0x91 0x92 0x92 0x93 0x93 0x94 0x94 0x95 0x95 0x95 0x96 0x96 0x97 0x97 0x98 0x98 0x99 0x99 0x9a 0x9a 0x9a 0x9b 0x9b 0x9c 0x9c 0x9d 0x9d 0x9e 0x9e 0x9e 0x9f 0x9f 0xa0 0xa0 0xa0 0xa1 0xa1 0xa2 0xa2 0xa2 0xa3 0xa3 0xa3 0xa4 0xa4 0xa5 0xa5 0xa5 0xa6 0xa6 0xa6 0xa7 0xa7 0xa7 0xa8 0xa8 0xa8 0xa9 0xa9 0xa9 0xaa 0xaa 0xaa 0xab 0xab 0xab 0xac 0xac 0xac 0xad 0xad 0xad 0xae 0xae 0xae 0xaf 0xaf 0xaf 0xb0 0xb0 0xb1 0xb1 0xb1 0xb2 0xb2 0xb2 0xb3 0xb3 0xb3 0xb4 0xb4 0xb5 0xb5 0xb5 0xb6 0xb6 0xb7 0xb7 0xb7 0xb8 0xb8 0xb8 0xb9 0xb9 0xba 0xba 0xba 0xbb 0xbb 0xbc 0xbc 0xbc 0xbd 0xbd 0xbd 0xbe 0xbe 0xbf 0xbf 0xbf 0xc0 0xc0 0xc0 0xc1 0xc1 0xc1 0xc2 0xc2 0xc2 0xc3 0xc3 0xc4 0xc4 0xc4 0xc5 0xc5 0xc5 0xc6 0xc6 0xc6 0xc6 0xc7 0xc7 0xc7 0xc8 0xc8 0xc8 0xc9 0xc9 0xc9 0xca 0xca 0xca 0xcb 0xcb 0xcb 0xcb 0xcc 0xcc 0xcc 0xcd 0xcd 0xcd 0xcd 0xce 0xce 0xce 0xcf 0xcf 0xcf 0xcf 0xd0 0xd0 0xd0 0xd1 0xd1 0xd1 0xd1 0xd2 0xd2 0xd2 0xd3 0xd3 0xd3 0xd3 0xd4 0xd4 0xd4 0xd4 0xd5 0xd5 0xd5 0xd6 0xd6 0xd6 0xd6 0xd7 0xd7 0xd7 0xd7 0xd8 0xd8 0xd8 0xd9 0xd9 0xd9 0xd9 0xda 0xda 0xda 0xda 0xdb 0xdb 0xdb 0xdb 0xdc 0xdc 0xdc 0xdc 0xdd 0xdd 0xdd 0xde 0xde 0xde 0xde 0xdf 0xdf 0xdf 0xdf 0xe0 0xe0 0xe0 0xe0 0xe1 0xe1 0xe1 0xe1 0xe2 0xe2 0xe2 0xe2 0xe3 0xe3 0xe3 0xe3 0xe4 0xe4 0xe4 0xe4 0xe5 0xe5 0xe5 0xe6 0xe6 0xe6 0xe6 0xe7 0xe7 0xe7 0xe7 0xe8 0xe8 0xe8 0xe8 0xe9 0xe9 0xe9 0xe9 0xea 0xea 0xea 0xea 0xeb 0xeb 0xeb 0xeb 0xec 0xec 0xec 0xec 0xed 0xed 0xed 0xed 0xee 0xee 0xee 0xee 0xee 0xef 0xef 0xef 0xef 0xf0 0xf0 0xf0 0xf0 0xf1 0xf1 0xf1 0xf1 0xf2 0xf2 0xf2 0xf2 0xf3 0xf3 0xf3 0xf3 0xf3 0xf4 0xf4 0xf4 0xf4 0xf5 0xf5 0xf5 0xf5 0xf6 0xf6 0xf6 0xf6 0xf6 0xf7 0xf7 0xf7 0xf7 0xf8 0xf8 0xf8 0xf8 0xf8 0xf9 0xf9 0xf9 0xf9 0xf9 0xfa 0xfa 0xfa 0xfa 0xfb 0xfb 0xfb 0xfb 0xfb 0xfc 0xfc 0xfc 0xfc 0xfc 0xfd 0xfd 0xfd 0xfd 0xfd 0xfe 0xfe 0xfe 0xfe 0xfe 0xff 0xff 0xff 0xff 0xff>; | |
| }; | |
| }; | |
| }; | |
| dc@54200000 { | |
| compatible = "nvidia,tegra124-dc"; | |
| reg = <0x0 0x54200000 0x0 0x40000>; | |
| interrupts = <0x0 0x49 0x4>; | |
| clocks = <0x2 0x1b 0x2 0xd3>; | |
| clock-names = "dc", "parent"; | |
| resets = <0x2 0x1b>; | |
| reset-names = "dc"; | |
| iommus = <0x4 0x1>; | |
| nvidia,head = <0x0>; | |
| status = "okay"; | |
| nvidia,dc-flags = <0x1>; | |
| nvidia,emc-clk-rate = <0xc28cb00>; | |
| nvidia,cmu-enable = <0x1>; | |
| nvidia,low-v-win = <0x2>; | |
| nvidia,fb-bpp = <0x20>; | |
| nvidia,fb-flags = <0x1>; | |
| }; | |
| dc@54240000 { | |
| compatible = "nvidia,tegra124-dc"; | |
| reg = <0x0 0x54240000 0x0 0x40000>; | |
| interrupts = <0x0 0x4a 0x4>; | |
| clocks = <0x2 0x1a 0x2 0xd3>; | |
| clock-names = "dc", "parent"; | |
| resets = <0x2 0x1a>; | |
| reset-names = "dc"; | |
| iommus = <0x4 0x2>; | |
| nvidia,head = <0x1>; | |
| status = "okay"; | |
| nvidia,dc-flags = <0x1>; | |
| nvidia,emc-clk-rate = <0x11e1a300>; | |
| nvidia,fb-bpp = <0x20>; | |
| nvidia,fb-flags = <0x1>; | |
| }; | |
| hdmi@54280000 { | |
| compatible = "nvidia,tegra124-hdmi"; | |
| reg = <0x0 0x54280000 0x0 0x40000>; | |
| interrupts = <0x0 0x4b 0x4>; | |
| clocks = <0x2 0x33 0x2 0xdd>; | |
| clock-names = "hdmi", "parent"; | |
| resets = <0x2 0x33>; | |
| reset-names = "hdmi"; | |
| status = "disabled"; | |
| }; | |
| cpu_edp { | |
| compatible = "nvidia,tegra124-cpu-edp-capping"; | |
| nvidia,freq_step = <0xc28cb0>; | |
| nvidia,edp_clk = "cpu_g"; | |
| nvidia,tegra-ppm-cdyn = <0xe7ef0 0x1558d8 0x210cf0 0x2e66e8>; | |
| nvidia,tegra-ppm-leakage_weights = <0x1c2 0x29e 0x366 0x3e8>; | |
| nvidia,tegra-ppm-min_leakage = <0x1e>; | |
| nvidia,tegra-ppm-leakage_coeffs = <0xed8bbc08 0xbc9fad6 0xfd9200f2 0x18a075 0x398066ed 0xde1481e1 0x6e6afe7 0xffbfd128 0xc4bbceca 0x1f92081f 0xf9a912d4 0x34b451 0x1474f5e2 0xf66dc81f 0x1e7311d 0xfff2574b 0x24bc4ab0 0xda080aad 0x8360b68 0xff9239eb 0x9180fe3d 0x71032a53 0xe7b77405 0x13e6c7c 0x6cb9836b 0x92d3d318 0x174a6c7b 0xfed5fe76 0xdce23453 0x22805ffe 0xf8b06c44 0x5b5529 0xe5c6394b 0x1b2ba582 0xf9cb9b0b 0x5e7b1b 0x50be5496 0xacd16a2e 0x12fe73af 0xfedfcf06 0xaed67439 0x52dc002e 0xed13b91c 0x11dc54a 0x1ab212ff 0xe51874f5 0x626ba9a 0xffa3bc1c 0x362a974 0xfc6fd628 0xd2ba77 0xfff30e5e 0xf5847a5b 0xb031f25 0xfd7452ee 0x280061 0xa965cf5 0xf4e9eb03 0x2909388 0xffd7be35 0xfc820665 0x3a3ef7a 0xff2826c3 0xd3447>; | |
| }; | |
| sor@54540000 { | |
| compatible = "nvidia,tegra124-sor"; | |
| reg = <0x0 0x54540000 0x0 0x40000>; | |
| interrupts = <0x0 0x4c 0x4>; | |
| clocks = <0x2 0xb6 0x2 0xdb 0x2 0x10f 0x2 0xc9>; | |
| clock-names = "sor", "parent", "dp", "safe"; | |
| resets = <0x2 0xb6>; | |
| reset-names = "sor"; | |
| status = "disabled"; | |
| }; | |
| dpaux@545c0000 { | |
| compatible = "nvidia,tegra124-dpaux"; | |
| reg = <0x0 0x545c0000 0x0 0x40000>; | |
| interrupts = <0x0 0x9f 0x4>; | |
| clocks = <0x2 0xb5 0x2 0x10f>; | |
| clock-names = "dpaux", "parent"; | |
| resets = <0x2 0xb5>; | |
| reset-names = "dpaux"; | |
| status = "disabled"; | |
| }; | |
| }; | |
| backlight { | |
| panel-a-wuxga-8-0-bl { | |
| status = "okay"; | |
| compatible = "a,wuxga-8-0-bl"; | |
| pwms = <0x5 0x1 0x9ce1>; | |
| max-brightness = <0xff>; | |
| default-brightness = <0xbf>; | |
| default-charge-brightness = <0x70>; | |
| bl-measured = <0x0 0x1 0x2 0x4 0x5 0x6 0x7 0x8 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x26 0x27 0x28 0x29 0x2a 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3d 0x3e 0x3f 0x40 0x41 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x70 0x71 0x72 0x73 0x73 0x74 0x75 0x75 0x76 0x77 0x78 0x7a 0x7b 0x7c 0x7d 0x7e 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa1 0xa2 0xa3 0xa4 0xa4 0xa5 0xa6 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbd 0xbe 0xbf 0xc0 0xc1 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf7 0xf8 0xf9 0xfa 0xfb 0xfb 0xfc 0xfc 0xfd 0xfd 0xfe 0xfe 0xff 0xff>; | |
| }; | |
| }; | |
| therm_est_sensor { | |
| compatible = "nvidia,therm-est"; | |
| #thermal-sensor-cells = <0x0>; | |
| status = "okay"; | |
| toffset = <0x2641>; | |
| polling-period = <0x44c>; | |
| tc1 = <0xa>; | |
| tc2 = <0x1>; | |
| use_activator = <0x1>; | |
| linux,phandle = <0x6>; | |
| phandle = <0x6>; | |
| subdevs@0 { | |
| device_type = "therm-est-subdev"; | |
| dev-data = "Tdiode_tegra"; | |
| coeffs = "2 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 -1 -7"; | |
| }; | |
| subdevs@1 { | |
| device_type = "therm-est-subdev"; | |
| dev-data = "Tboard_tegra"; | |
| coeffs = "-11 -7 -5 -3 -3 -2 -1 0 0 0 1 1 1 2 2 3 4 6 11 18"; | |
| }; | |
| }; | |
| thermal-zones { | |
| therm_est { | |
| polling-delay = <0x0>; | |
| polling-delay-passive = <0x3a98>; | |
| thermal-sensors = <0x6>; | |
| trips { | |
| skin_trip { | |
| temperature = <0xa7f8>; | |
| hysteresis = <0x0>; | |
| type = "passive"; | |
| writable; | |
| linux,phandle = <0x7>; | |
| phandle = <0x7>; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0x7>; | |
| cdev-type = "skin-balanced"; | |
| cooling-device = <0x8 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| thermal-zone-params { | |
| governor-name = "adaptive_skin"; | |
| tskin_tran_threshold = <0x1f4>; | |
| tskin_std_threshold = <0x3e8>; | |
| target_state_tdp = <0x7>; | |
| tj_tran_threshold = <0x7d0>; | |
| tj_std_threshold = <0xbb8>; | |
| tj_std_fup_threshold = <0x1388>; | |
| }; | |
| }; | |
| cpu { | |
| polling-delay-passive = <0x3e8>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0x9 0x0>; | |
| }; | |
| mem { | |
| polling-delay-passive = <0x3e8>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0x9 0x1>; | |
| }; | |
| gpu { | |
| polling-delay-passive = <0x3e8>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0x9 0x2>; | |
| }; | |
| pllx { | |
| polling-delay-passive = <0x3e8>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0x9 0x3>; | |
| }; | |
| }; | |
| aliases { | |
| i2c0 = "/i2c@7000c000"; | |
| i2c1 = "/i2c@7000c400"; | |
| i2c2 = "/i2c@7000c500"; | |
| i2c3 = "/i2c@7000c700"; | |
| i2c4 = "/i2c@7000d000"; | |
| i2c5 = "/i2c@7000d100"; | |
| serial0 = "/serial@70006000"; | |
| serial1 = "/serial@70006040"; | |
| serial2 = "/serial@70006200"; | |
| serial3 = "/serial@70006300"; | |
| spi0 = "/spi@7000d400"; | |
| spi1 = "/spi@7000d600"; | |
| spi2 = "/spi@7000d800"; | |
| spi3 = "/spi@7000da00"; | |
| spi4 = "/spi@7000dc00"; | |
| spi5 = "/spi@7000de00"; | |
| rtc0 = "/i2c@0,7000d000/pmic@40"; | |
| rtc1 = "/rtc@0,7000e000"; | |
| }; | |
| mc { | |
| compatible = "nvidia,tegra-mc"; | |
| reg-ranges = <0x9>; | |
| reg = <0x0 0x70019000 0x0 0xc 0x0 0x70019050 0x0 0x19c 0x0 0x70019200 0x0 0x24 0x0 0x7001929c 0x0 0x1b8 0x0 0x70019464 0x0 0x198 0x0 0x70019604 0x0 0x3b0 0x0 0x700199bc 0x0 0x20 0x0 0x700199f8 0x0 0x8c 0x0 0x70019ab4 0x0 0x54c>; | |
| interrupts = <0x0 0x4d 0x4>; | |
| int_count = <0x8>; | |
| int_mask = <0x13d40>; | |
| channels = <0x1>; | |
| }; | |
| pinmux@70000868 { | |
| compatible = "nvidia,tegra124-pinmux"; | |
| reg = <0x0 0x70000868 0x0 0x164 0x0 0x70003000 0x0 0x434 0x0 0x70000820 0x0 0x8>; | |
| #gpio-range-cells = <0x3>; | |
| linux,phandle = <0xa>; | |
| phandle = <0xa>; | |
| }; | |
| gpio@6000d000 { | |
| compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; | |
| reg = <0x0 0x6000d000 0x0 0x1000>; | |
| interrupts = <0x0 0x20 0x4 0x0 0x21 0x4 0x0 0x22 0x4 0x0 0x23 0x4 0x0 0x37 0x4 0x0 0x57 0x4 0x0 0x59 0x4 0x0 0x7d 0x4>; | |
| #gpio-cells = <0x2>; | |
| gpio-controller; | |
| #interrupt-cells = <0x2>; | |
| interrupt-controller; | |
| gpio-ranges = <0xa 0x0 0x0 0xfb>; | |
| linux,phandle = <0x3>; | |
| phandle = <0x3>; | |
| }; | |
| se@70012000 { | |
| compatible = "nvidia,tegra124-se"; | |
| reg = <0x0 0x70012000 0x0 0x2000 0x0 0x7000e400 0x0 0x400>; | |
| interrupts = <0x0 0x3a 0x4>; | |
| }; | |
| memory-controller@70019000 { | |
| compatible = "nvidia,tegra124-mc"; | |
| reg = <0x0 0x70019000 0x0 0x1000>; | |
| #asids = <0x80>; | |
| dma-window = <0x0 0x80000000 0x0 0x7ff00000>; | |
| #iommu-cells = <0x1>; | |
| swgid-mask = <0x1 0xfffecdcf>; | |
| #num-translation-enable = <0x4>; | |
| #num-asid-security = <0x8>; | |
| ptc-cache-size = <0x8000>; | |
| clocks = <0x2 0x20>; | |
| clock-names = "mc"; | |
| interrupts = <0x0 0x4d 0x4>; | |
| linux,phandle = <0x4>; | |
| phandle = <0x4>; | |
| address-space-prop { | |
| common { | |
| iova-start = <0x0 0x80000000>; | |
| iova-size = <0x0 0x7ff00000>; | |
| alignment = <0xfffff>; | |
| num-pf-page = <0x0>; | |
| gap-page = <0x1>; | |
| }; | |
| ppcs { | |
| iova-start = <0x0 0x80000000>; | |
| iova-size = <0x0 0x7ff00000>; | |
| alignment = <0xfffff>; | |
| num-pf-page = <0x1>; | |
| gap-page = <0x1>; | |
| }; | |
| dc { | |
| iova-start = <0x0 0x10000>; | |
| iova-size = <0x0 0xfffeffff>; | |
| alignment = <0xfffff>; | |
| num-pf-page = <0x0>; | |
| gap-page = <0x0>; | |
| }; | |
| gpu { | |
| iova-start = <0x0 0x100000>; | |
| iova-size = <0x0 0xffefffff>; | |
| alignment = <0xfffff>; | |
| num-pf-page = <0x0>; | |
| gap-page = <0x0>; | |
| }; | |
| }; | |
| }; | |
| dma@60020000 { | |
| compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; | |
| reg = <0x0 0x60020000 0x0 0x1400>; | |
| interrupts = <0x0 0x68 0x4 0x0 0x69 0x4 0x0 0x6a 0x4 0x0 0x6b 0x4 0x0 0x6c 0x4 0x0 0x6d 0x4 0x0 0x6e 0x4 0x0 0x6f 0x4 0x0 0x70 0x4 0x0 0x71 0x4 0x0 0x72 0x4 0x0 0x73 0x4 0x0 0x74 0x4 0x0 0x75 0x4 0x0 0x76 0x4 0x0 0x77 0x4 0x0 0x80 0x4 0x0 0x81 0x4 0x0 0x82 0x4 0x0 0x83 0x4 0x0 0x84 0x4 0x0 0x85 0x4 0x0 0x86 0x4 0x0 0x87 0x4 0x0 0x88 0x4 0x0 0x89 0x4 0x0 0x8a 0x4 0x0 0x8b 0x4 0x0 0x8c 0x4 0x0 0x8d 0x4 0x0 0x8e 0x4 0x0 0x8f 0x4>; | |
| #dma-cells = <0x1>; | |
| clocks = <0x2 0x22>; | |
| resets = <0x2 0x22>; | |
| reset-names = "dma"; | |
| linux,phandle = <0xb>; | |
| phandle = <0xb>; | |
| }; | |
| serial@70006000 { | |
| compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; | |
| reg = <0x0 0x70006000 0x0 0x40>; | |
| reg-shift = <0x2>; | |
| interrupts = <0x0 0x24 0x4>; | |
| nvidia,dma-request-selector = <0xb 0x8>; | |
| iommus = <0x4 0x8>; | |
| status = "disabled"; | |
| dmas = <0xb 0x8 0xb 0x8>; | |
| dma-names = "rx", "tx"; | |
| clocks = <0x2 0x6>; | |
| resets = <0x2 0x6>; | |
| reset-names = "serial"; | |
| }; | |
| serial@70006040 { | |
| compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; | |
| reg = <0x0 0x70006040 0x0 0x40>; | |
| reg-shift = <0x2>; | |
| interrupts = <0x0 0x25 0x4>; | |
| nvidia,dma-request-selector = <0xb 0x9>; | |
| iommus = <0x4 0x8>; | |
| status = "disabled"; | |
| dmas = <0xb 0x9 0xb 0x9>; | |
| dma-names = "rx", "tx"; | |
| clocks = <0x2 0xc0>; | |
| resets = <0x2 0x7>; | |
| reset-names = "serial"; | |
| }; | |
| serial@70006200 { | |
| compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; | |
| reg = <0x0 0x70006200 0x0 0x40>; | |
| reg-shift = <0x2>; | |
| interrupts = <0x0 0x2e 0x4>; | |
| nvidia,dma-request-selector = <0xb 0xa>; | |
| iommus = <0x4 0x8>; | |
| status = "disabled"; | |
| dmas = <0xb 0xa 0xb 0xa>; | |
| dma-names = "rx", "tx"; | |
| clocks = <0x2 0x37>; | |
| resets = <0x2 0x37>; | |
| reset-names = "serial"; | |
| }; | |
| serial@70006300 { | |
| compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; | |
| reg = <0x0 0x70006300 0x0 0x40>; | |
| reg-shift = <0x2>; | |
| interrupts = <0x0 0x5a 0x4>; | |
| nvidia,dma-request-selector = <0xb 0x13>; | |
| iommus = <0x4 0x8>; | |
| status = "disabled"; | |
| dmas = <0xb 0x13 0xb 0x13>; | |
| dma-names = "rx", "tx"; | |
| clocks = <0x2 0x41>; | |
| resets = <0x2 0x41>; | |
| reset-names = "serial"; | |
| }; | |
| pwm@7000a000 { | |
| compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; | |
| reg = <0x0 0x7000a000 0x0 0x100>; | |
| #pwm-cells = <0x2>; | |
| status = "disabled"; | |
| clocks = <0x2 0x11>; | |
| resets = <0x2 0x11>; | |
| reset-names = "pwm"; | |
| linux,phandle = <0x5>; | |
| phandle = <0x5>; | |
| }; | |
| i2c@7000c000 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; | |
| reg = <0x0 0x7000c000 0x0 0x100>; | |
| interrupts = <0x0 0x26 0x4>; | |
| scl-gpio = <0x3 0x14 0x0>; | |
| sda-gpio = <0x3 0x15 0x0>; | |
| iommus = <0x4 0x8>; | |
| status = "disabled"; | |
| clock-frequency = <0x61a80>; | |
| clocks = <0x2 0xc>; | |
| clock-names = "div-clk"; | |
| resets = <0x2 0xc>; | |
| reset-names = "i2c"; | |
| dmas = <0xb 0x15 0xb 0x15>; | |
| dma-names = "rx", "tx"; | |
| }; | |
| i2c@7000c400 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; | |
| reg = <0x0 0x7000c400 0x0 0x100>; | |
| interrupts = <0x0 0x54 0x4>; | |
| scl-gpio = <0x3 0x9d 0x0>; | |
| sda-gpio = <0x3 0x9e 0x0>; | |
| iommus = <0x4 0x8>; | |
| status = "disabled"; | |
| clock-frequency = <0x186a0>; | |
| clocks = <0x2 0x36>; | |
| clock-names = "div-clk"; | |
| resets = <0x2 0x36>; | |
| reset-names = "i2c"; | |
| dmas = <0xb 0x16 0xb 0x16>; | |
| dma-names = "rx", "tx"; | |
| }; | |
| i2c@7000c500 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; | |
| reg = <0x0 0x7000c500 0x0 0x100>; | |
| interrupts = <0x0 0x5c 0x4>; | |
| scl-gpio = <0x3 0xd9 0x0>; | |
| sda-gpio = <0x3 0xda 0x0>; | |
| iommus = <0x4 0x8>; | |
| status = "disabled"; | |
| clock-frequency = <0x61a80>; | |
| clocks = <0x2 0x43>; | |
| clock-names = "div-clk"; | |
| resets = <0x2 0x43>; | |
| reset-names = "i2c"; | |
| dmas = <0xb 0x17 0xb 0x17>; | |
| dma-names = "rx", "tx"; | |
| }; | |
| i2c@7000c700 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; | |
| reg = <0x0 0x7000c700 0x0 0x100>; | |
| interrupts = <0x0 0x78 0x4>; | |
| scl-gpio = <0x3 0xac 0x0>; | |
| sda-gpio = <0x3 0xad 0x0>; | |
| iommus = <0x4 0x8>; | |
| status = "disabled"; | |
| clock-frequency = <0x186a0>; | |
| clocks = <0x2 0x67>; | |
| clock-names = "div-clk"; | |
| resets = <0x2 0x67>; | |
| reset-names = "i2c"; | |
| dmas = <0xb 0x1a 0xb 0x1a>; | |
| dma-names = "rx", "tx"; | |
| }; | |
| i2c@7000d000 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; | |
| reg = <0x0 0x7000d000 0x0 0x100>; | |
| interrupts = <0x0 0x35 0x4>; | |
| nvidia,require-cldvfs-clock; | |
| scl-gpio = <0x3 0xce 0x0>; | |
| sda-gpio = <0x3 0xcf 0x0>; | |
| iommus = <0x4 0x8>; | |
| status = "disabled"; | |
| clock-frequency = <0x61a80>; | |
| clocks = <0x2 0x2f>; | |
| clock-names = "div-clk"; | |
| resets = <0x2 0x2f>; | |
| reset-names = "i2c"; | |
| dmas = <0xb 0x18 0xb 0x18>; | |
| dma-names = "rx", "tx"; | |
| }; | |
| i2c@7000d100 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; | |
| reg = <0x0 0x7000d100 0x0 0x100>; | |
| interrupts = <0x0 0x3f 0x4>; | |
| iommus = <0x4 0x8>; | |
| status = "disabled"; | |
| clock-frequency = <0x61a80>; | |
| clocks = <0x2 0xa6>; | |
| clock-names = "div-clk"; | |
| resets = <0x2 0xa6>; | |
| reset-names = "i2c"; | |
| dmas = <0xb 0x1e 0xb 0x1e>; | |
| dma-names = "rx", "tx"; | |
| }; | |
| spi@7000d400 { | |
| compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | |
| reg = <0x0 0x7000d400 0x0 0x200>; | |
| interrupts = <0x0 0x3b 0x4>; | |
| nvidia,dma-request-selector = <0xb 0xf>; | |
| iommus = <0x4 0x8>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| clocks = <0x2 0x29>; | |
| status = "disabled"; | |
| dmas = <0xb 0xf 0xb 0xf>; | |
| dma-names = "rx", "tx"; | |
| nvidia,clk-parents = "pll_p", "clk_m"; | |
| clock-names = "spi"; | |
| resets = <0x2 0x29>; | |
| reset-names = "spi"; | |
| }; | |
| spi@7000d600 { | |
| compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | |
| reg = <0x0 0x7000d600 0x0 0x200>; | |
| interrupts = <0x0 0x52 0x4>; | |
| nvidia,dma-request-selector = <0xb 0x10>; | |
| iommus = <0x4 0x8>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| clocks = <0x2 0x2c>; | |
| status = "disabled"; | |
| dmas = <0xb 0x10 0xb 0x10>; | |
| dma-names = "rx", "tx"; | |
| nvidia,clk-parents = "pll_p", "clk_m"; | |
| clock-names = "spi"; | |
| resets = <0x2 0x2c>; | |
| reset-names = "spi"; | |
| }; | |
| spi@7000d800 { | |
| compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | |
| reg = <0x0 0x7000d800 0x0 0x200>; | |
| interrupts = <0x0 0x53 0x4>; | |
| nvidia,dma-request-selector = <0xb 0x11>; | |
| iommus = <0x4 0x8>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| clocks = <0x2 0x2e>; | |
| status = "disabled"; | |
| dmas = <0xb 0x11 0xb 0x11>; | |
| dma-names = "rx", "tx"; | |
| nvidia,clk-parents = "pll_p", "clk_m"; | |
| clock-names = "spi"; | |
| resets = <0x2 0x2e>; | |
| reset-names = "spi"; | |
| }; | |
| spi@7000da00 { | |
| compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | |
| reg = <0x0 0x7000da00 0x0 0x200>; | |
| interrupts = <0x0 0x5d 0x4>; | |
| nvidia,dma-request-selector = <0xb 0x12>; | |
| iommus = <0x4 0x8>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| clocks = <0x2 0x44>; | |
| status = "disabled"; | |
| dmas = <0xb 0x12 0xb 0x12>; | |
| dma-names = "rx", "tx"; | |
| nvidia,clk-parents = "pll_p", "clk_m"; | |
| clock-names = "spi"; | |
| resets = <0x2 0x44>; | |
| reset-names = "spi"; | |
| }; | |
| spi@7000dc00 { | |
| compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | |
| reg = <0x0 0x7000dc00 0x0 0x200>; | |
| interrupts = <0x0 0x5e 0x4>; | |
| nvidia,dma-request-selector = <0xb 0x1b>; | |
| iommus = <0x4 0x8>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| clocks = <0x2 0x68>; | |
| status = "disabled"; | |
| dmas = <0xb 0x1b 0xb 0x1b>; | |
| dma-names = "rx", "tx"; | |
| nvidia,clk-parents = "pll_p", "clk_m"; | |
| clock-names = "spi"; | |
| resets = <0x2 0x68>; | |
| reset-names = "spi"; | |
| }; | |
| spi@7000de00 { | |
| compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | |
| reg = <0x0 0x7000de00 0x0 0x200>; | |
| interrupts = <0x0 0x4f 0x4>; | |
| nvidia,dma-request-selector = <0xb 0x1c>; | |
| iommus = <0x4 0x8>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| clocks = <0x2 0x69>; | |
| status = "disabled"; | |
| dmas = <0xb 0x1c 0xb 0x1c>; | |
| dma-names = "rx", "tx"; | |
| nvidia,clk-parents = "pll_p", "clk_m"; | |
| clock-names = "spi"; | |
| resets = <0x2 0x69>; | |
| reset-names = "spi"; | |
| }; | |
| pmc@7000e400 { | |
| compatible = "nvidia,tegra124-pmc"; | |
| reg = <0x0 0x7000e400 0x0 0x400>; | |
| clocks = <0x2 0x105 0xc>; | |
| clock-names = "pclk", "clk32k_in"; | |
| }; | |
| efuse@7000f800 { | |
| compatible = "nvidia,tegra124-efuse"; | |
| reg = <0x0 0x7000f800 0x0 0x400>; | |
| }; | |
| clocks { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| clock { | |
| compatible = "fixed-clock"; | |
| reg = <0x0>; | |
| #clock-cells = <0x0>; | |
| clock-frequency = <0x8000>; | |
| linux,phandle = <0xc>; | |
| phandle = <0xc>; | |
| }; | |
| }; | |
| timer@60005000 { | |
| compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; | |
| reg = <0x0 0x60005000 0x0 0x400>; | |
| interrupts = <0x0 0x0 0x4 0x0 0x1 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x79 0x4 0x0 0x7a 0x4>; | |
| clocks = <0x2 0x5>; | |
| }; | |
| rtc { | |
| compatible = "nvidia,tegra-rtc"; | |
| reg = <0x0 0x7000e000 0x0 0x100>; | |
| interrupts = <0x0 0x2 0x4>; | |
| clocks = <0x2 0x4>; | |
| }; | |
| ahub@70300000 { | |
| compatible = "nvidia,tegra124-ahub"; | |
| reg = <0x0 0x70300000 0x0 0x200 0x0 0x70300800 0x0 0x800 0x0 0x70300200 0x0 0x600>; | |
| interrupts = <0x0 0x67 0x4>; | |
| dmas = <0xb 0x1 0xb 0x1 0xb 0x2 0xb 0x2 0xb 0x3 0xb 0x3 0xb 0x4 0xb 0x4 0xb 0x6 0xb 0x6 0xb 0x7 0xb 0x7 0xb 0xc 0xb 0xc 0xb 0xd 0xb 0xd 0xb 0xe 0xb 0xe 0xb 0x1d 0xb 0x1d>; | |
| dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", "rx9", "tx9"; | |
| status = "disabled"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges; | |
| clocks = <0x2 0x6a 0x2 0x6b>; | |
| clock-names = "d_audio", "apbif"; | |
| resets = <0x2 0x6a 0x2 0x6b 0x2 0x1e 0x2 0xb 0x2 0x12 0x2 0x65 0x2 0x66 0x2 0x6c 0x2 0x6d 0x2 0x6e 0x2 0xa 0x2 0x99 0x2 0xb9 0x2 0x9a 0x2 0xb4 0x2 0xba 0x2 0xbb 0x2 0xbc 0x2 0xbd 0x2 0xbe 0x2 0xbf>; | |
| reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", "i2s3", "i2s4", "dam0", "dam1", "dam2", "spdif", "amx", "amx1", "adx", "adx1", "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; | |
| i2s@70301000 { | |
| compatible = "nvidia,tegra124-i2s"; | |
| reg = <0x0 0x70301000 0x0 0x100>; | |
| interrupts = <0x0 0x67 0x4>; | |
| nvidia,ahub-cif-ids = <0x4 0x4>; | |
| nvidia,ahub-i2s-id = <0x0>; | |
| status = "disabled"; | |
| clocks = <0x2 0x1e>; | |
| resets = <0x2 0x1e>; | |
| reset-names = "i2s"; | |
| }; | |
| i2s@70301100 { | |
| compatible = "nvidia,tegra124-i2s"; | |
| reg = <0x0 0x70301100 0x0 0x100>; | |
| interrupts = <0x0 0x67 0x4>; | |
| nvidia,ahub-cif-ids = <0x5 0x5>; | |
| nvidia,ahub-i2s-id = <0x1>; | |
| status = "disabled"; | |
| clocks = <0x2 0xb>; | |
| resets = <0x2 0xb>; | |
| reset-names = "i2s"; | |
| }; | |
| i2s@70301200 { | |
| compatible = "nvidia,tegra124-i2s"; | |
| reg = <0x0 0x70301200 0x0 0x100>; | |
| interrupts = <0x0 0x67 0x4>; | |
| nvidia,ahub-cif-ids = <0x6 0x6>; | |
| nvidia,ahub-i2s-id = <0x2>; | |
| status = "disabled"; | |
| clocks = <0x2 0x12>; | |
| resets = <0x2 0x12>; | |
| reset-names = "i2s"; | |
| }; | |
| i2s@70301300 { | |
| compatible = "nvidia,tegra124-i2s"; | |
| reg = <0x0 0x70301300 0x0 0x100>; | |
| interrupts = <0x0 0x67 0x4>; | |
| nvidia,ahub-cif-ids = <0x7 0x7>; | |
| nvidia,ahub-i2s-id = <0x3>; | |
| status = "disabled"; | |
| clocks = <0x2 0x65>; | |
| resets = <0x2 0x65>; | |
| reset-names = "i2s"; | |
| }; | |
| i2s@70301400 { | |
| compatible = "nvidia,tegra124-i2s"; | |
| reg = <0x0 0x70301400 0x0 0x100>; | |
| interrupts = <0x0 0x67 0x4>; | |
| nvidia,ahub-cif-ids = <0x8 0x8>; | |
| nvidia,ahub-i2s-id = <0x4>; | |
| status = "disabled"; | |
| clocks = <0x2 0x66>; | |
| resets = <0x2 0x66>; | |
| reset-names = "i2s"; | |
| }; | |
| amx@70303000 { | |
| compatible = "nvidia,tegra124-amx"; | |
| reg = <0x70303000 0x100>; | |
| status = "disabled"; | |
| }; | |
| amx@70303100 { | |
| compatible = "nvidia,tegra124-amx"; | |
| reg = <0x70303100 0x100>; | |
| status = "disabled"; | |
| }; | |
| adx@70303800 { | |
| compatible = "nvidia,tegra124-adx"; | |
| reg = <0x70303800 0x100>; | |
| status = "disabled"; | |
| }; | |
| adx@70303900 { | |
| compatible = "nvidia,tegra124-adx"; | |
| reg = <0x70303900 0x100>; | |
| status = "disabled"; | |
| }; | |
| spdif@70306000 { | |
| compatible = "nvidia,tegra124-spdif"; | |
| reg = <0x70306000 0x100>; | |
| status = "disabled"; | |
| }; | |
| dam@70302000 { | |
| compatible = "nvidia,tegra124-dam"; | |
| reg = <0x70302000 0x200>; | |
| nvidia,ahub-dam-id = <0x0>; | |
| status = "disabled"; | |
| }; | |
| dam@70302200 { | |
| compatible = "nvidia,tegra124-dam"; | |
| reg = <0x70302200 0x200>; | |
| nvidia,ahub-dam-id = <0x1>; | |
| status = "disabled"; | |
| }; | |
| dam@70302400 { | |
| compatible = "nvidia,tegra124-dam"; | |
| reg = <0x70302400 0x200>; | |
| nvidia,ahub-dam-id = <0x2>; | |
| status = "disabled"; | |
| }; | |
| afc@70307000 { | |
| compatible = "nvidia,tegra124-afc"; | |
| reg = <0x70307000 0x100>; | |
| nvidia,ahub-afc-id = <0x0>; | |
| status = "disabled"; | |
| }; | |
| afc@70307100 { | |
| compatible = "nvidia,tegra124-afc"; | |
| reg = <0x70307100 0x100>; | |
| nvidia,ahub-afc-id = <0x1>; | |
| status = "disabled"; | |
| }; | |
| afc@70307200 { | |
| compatible = "nvidia,tegra124-afc"; | |
| reg = <0x70307200 0x100>; | |
| nvidia,ahub-afc-id = <0x2>; | |
| status = "disabled"; | |
| }; | |
| afc@70307300 { | |
| compatible = "nvidia,tegra124-afc"; | |
| reg = <0x70307300 0x100>; | |
| nvidia,ahub-afc-id = <0x3>; | |
| status = "disabled"; | |
| }; | |
| afc@70307400 { | |
| compatible = "nvidia,tegra124-afc"; | |
| reg = <0x70307400 0x100>; | |
| nvidia,ahub-afc-id = <0x4>; | |
| status = "disabled"; | |
| }; | |
| afc@70307500 { | |
| compatible = "nvidia,tegra124-afc"; | |
| reg = <0x70307500 0x100>; | |
| nvidia,ahub-afc-id = <0x5>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| hda@70030000 { | |
| compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; | |
| reg = <0x0 0x70030000 0x0 0x10000>; | |
| interrupts = <0x0 0x51 0x4>; | |
| clocks = <0x2 0x7d 0x2 0x80 0x2 0x6f>; | |
| clock-names = "hda", "hda2hdmi", "hda2codec_2x"; | |
| resets = <0x2 0x7d 0x2 0x80 0x2 0x6f>; | |
| reset-names = "hda", "hda2hdmi", "hda2codec_2x"; | |
| status = "disabled"; | |
| }; | |
| host1x { | |
| compatible = "nvidia,tegra124-host1x", "simple-bus"; | |
| reg = <0x0 0x50000000 0x0 0x34000>; | |
| interrupts = <0x0 0x41 0x4 0x0 0x43 0x4>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges = <0x53000000 0x0 0x53000000 0x6000000 0x60001000 0x0 0x60001000 0xe200>; | |
| linux,phandle = <0xd>; | |
| phandle = <0xd>; | |
| vi { | |
| compatible = "nvidia,tegra124-vi"; | |
| reg = <0x54080000 0x40000>; | |
| interrupts = <0x0 0x45 0x4>; | |
| iommus = <0x4 0x19>; | |
| }; | |
| isp@54600000 { | |
| compatible = "nvidia,tegra124-isp"; | |
| reg = <0x54600000 0x40000>; | |
| interrupts = <0x0 0x47 0x4>; | |
| iommus = <0x4 0x10>; | |
| }; | |
| isp@54680000 { | |
| compatible = "nvidia,tegra124-isp"; | |
| reg = <0x54680000 0x40000>; | |
| interrupts = <0x0 0x46 0x4>; | |
| iommus = <0x4 0x10>; | |
| }; | |
| dc@54200000 { | |
| compatible = "nvidia,tegra124-dc"; | |
| reg = <0x54200000 0x40000>; | |
| interrupts = <0x0 0x49 0x4>; | |
| iommus = <0x4 0x1>; | |
| status = "disabled"; | |
| rgb { | |
| status = "disabled"; | |
| }; | |
| }; | |
| dc@54240000 { | |
| compatible = "nvidia,tegra124-dc"; | |
| reg = <0x54240000 0x40000>; | |
| interrupts = <0x0 0x4a 0x4>; | |
| iommus = <0x4 0x2>; | |
| status = "disabled"; | |
| rgb { | |
| status = "disabled"; | |
| }; | |
| }; | |
| hdmi { | |
| compatible = "nvidia,tegra124-hdmi"; | |
| reg = <0x54280000 0x40000>; | |
| interrupts = <0x0 0x4b 0x4>; | |
| status = "okay"; | |
| }; | |
| dsi { | |
| compatible = "nvidia,tegra124-dsi"; | |
| reg = <0x54300000 0x40000 0x54400000 0x40000>; | |
| status = "disabled"; | |
| }; | |
| vic { | |
| compatible = "nvidia,tegra124-vic"; | |
| reg = <0x54340000 0x40000>; | |
| iommus = <0x4 0x18>; | |
| }; | |
| msenc { | |
| compatible = "nvidia,tegra124-msenc"; | |
| reg = <0x544c0000 0x40000>; | |
| iommus = <0x4 0x7>; | |
| }; | |
| tsec { | |
| compatible = "nvidia,tegra124-tsec"; | |
| reg = <0x54500000 0x40000>; | |
| iommus = <0x4 0x11>; | |
| }; | |
| sor { | |
| compatible = "nvidia,tegra124-sor"; | |
| reg = <0x54540000 0x40000>; | |
| status = "disabled"; | |
| }; | |
| dpaux { | |
| compatible = "nvidia,tegra124-dpaux"; | |
| reg = <0x545c0000 0x40000>; | |
| interrupts = <0x0 0x9f 0x4>; | |
| status = "disabled"; | |
| }; | |
| nvavp { | |
| compatible = "nvidia,tegra124-nvavp"; | |
| interrupts = <0x0 0x4 0x4>; | |
| reg = <0x60001000 0xe200>; | |
| }; | |
| }; | |
| gk20a { | |
| compatible = "nvidia,tegra124-gk20a"; | |
| nvidia,host1x = <0xd>; | |
| reg = <0x0 0x57000000 0x0 0x1000000 0x0 0x58000000 0x0 0x1000000 0x0 0x538f0000 0x0 0x1000>; | |
| interrupts = <0x0 0x9d 0x4 0x0 0x9e 0x4>; | |
| iommus = <0x4 0x13>; | |
| access-vpr-phys; | |
| }; | |
| xusb@70090000 { | |
| compatible = "nvidia,tegra124-xhci"; | |
| reg = <0x0 0x70090000 0x0 0x8000 0x0 0x70098000 0x0 0x1000 0x0 0x70099000 0x0 0x1000 0x0 0x7009f000 0x0 0x1000>; | |
| interrupts = <0x0 0x27 0x4 0x0 0x28 0x4 0x0 0x31 0x4 0x0 0x61 0x4 0x0 0x15 0x4>; | |
| status = "disable"; | |
| }; | |
| mipical { | |
| compatible = "nvidia,tegra124-mipical"; | |
| reg = <0x0 0x700e3000 0x0 0x100>; | |
| }; | |
| pcie-controller { | |
| compatible = "nvidia,tegra124-pcie"; | |
| device_type = "pci"; | |
| reg = <0x0 0x1003000 0x0 0x800 0x0 0x1003800 0x0 0x800 0x0 0x2000000 0x0 0x10000000>; | |
| reg-names = "pads", "afi", "cs"; | |
| interrupts = <0x0 0x62 0x4 0x0 0x63 0x4>; | |
| interrupt-names = "intr", "msi"; | |
| #interrupt-cells = <0x1>; | |
| interrupt-map-mask = <0x0 0x0 0x0 0x0>; | |
| interrupt-map = <0x0 0x0 0x0 0x0 0x1 0x0 0x62 0x4>; | |
| bus-range = <0x0 0xff>; | |
| #address-cells = <0x3>; | |
| #size-cells = <0x2>; | |
| ranges = <0x82000000 0x0 0x1000000 0x0 0x1000000 0x0 0x1000 0x82000000 0x0 0x1001000 0x0 0x1001000 0x0 0x1000 0x81000000 0x0 0x0 0x0 0x12000000 0x0 0x10000 0x82000000 0x0 0x13000000 0x0 0x13000000 0x0 0xd000000 0xc2000000 0x0 0x20000000 0x0 0x20000000 0x0 0x20000000>; | |
| status = "disabled"; | |
| pci@1,0 { | |
| device_type = "pci"; | |
| assigned-addresses = <0x82000800 0x0 0x1000000 0x0 0x1000>; | |
| reg = <0x800 0x0 0x0 0x0 0x0>; | |
| status = "disabled"; | |
| #address-cells = <0x3>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| nvidia,num-lanes = <0x4>; | |
| }; | |
| pci@2,0 { | |
| device_type = "pci"; | |
| assigned-addresses = <0x82001000 0x0 0x1001000 0x0 0x1000>; | |
| reg = <0x1000 0x0 0x0 0x0 0x0>; | |
| status = "disabled"; | |
| #address-cells = <0x3>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| nvidia,num-lanes = <0x1>; | |
| }; | |
| }; | |
| sata@70020000 { | |
| compatible = "nvidia,tegra124-ahci"; | |
| reg = <0x0 0x70027000 0x0 0x2000 0x0 0x70020000 0x0 0x7000>; | |
| interrupts = <0x0 0x17 0x4>; | |
| status = "disabled"; | |
| clocks = <0x2 0x7c 0x2 0x7b 0x2 0x10d 0x2 0xe7>; | |
| clock-names = "sata", "sata-oob", "cml1", "pll_e"; | |
| resets = <0x2 0x7c 0x2 0x7b 0x2 0x81>; | |
| reset-names = "sata", "sata-oob", "sata-cold"; | |
| phys = <0xe 0x1>; | |
| phy-names = "sata-phy"; | |
| }; | |
| psci { | |
| compatible = "arm,psci"; | |
| method = "smc"; | |
| cpu_suspend = <0x84000001>; | |
| cpu_on = <0x84000003>; | |
| }; | |
| sdhci@700b0600 { | |
| compatible = "nvidia,tegra124-sdhci"; | |
| reg = <0x0 0x700b0600 0x0 0x200>; | |
| interrupts = <0x0 0x1f 0x4>; | |
| iommus = <0x4 0x17>; | |
| status = "disabled"; | |
| clocks = <0x2 0xf>; | |
| resets = <0x2 0xf>; | |
| reset-names = "sdhci"; | |
| }; | |
| sdhci@700b0400 { | |
| compatible = "nvidia,tegra124-sdhci"; | |
| reg = <0x0 0x700b0400 0x0 0x200>; | |
| interrupts = <0x0 0x13 0x4>; | |
| iommus = <0x4 0x16>; | |
| status = "disabled"; | |
| clocks = <0x2 0x45>; | |
| resets = <0x2 0x45>; | |
| reset-names = "sdhci"; | |
| }; | |
| sdhci@700b0200 { | |
| compatible = "nvidia,tegra124-sdhci"; | |
| reg = <0x0 0x700b0200 0x0 0x200>; | |
| interrupts = <0x0 0xf 0x4>; | |
| iommus = <0x4 0x15>; | |
| status = "disabled"; | |
| clocks = <0x2 0x9>; | |
| resets = <0x2 0x9>; | |
| reset-names = "sdhci"; | |
| }; | |
| sdhci@700b0000 { | |
| compatible = "nvidia,tegra124-sdhci"; | |
| reg = <0x0 0x700b0000 0x0 0x200>; | |
| interrupts = <0x0 0xe 0x4>; | |
| iommus = <0x4 0x14>; | |
| status = "disabled"; | |
| clocks = <0x2 0xe>; | |
| resets = <0x2 0xe>; | |
| reset-names = "sdhci"; | |
| }; | |
| tegra_cec { | |
| compatible = "nvidia,tegra124-cec"; | |
| reg = <0x0 0x70015000 0x0 0x1000>; | |
| interrupts = <0x0 0x3 0x4>; | |
| status = "okay"; | |
| }; | |
| ptm@7081C000 { | |
| compatible = "nvidia,ptm"; | |
| reg = <0x0 0x7081c000 0x0 0x1000 0x0 0x7081d000 0x0 0x1000 0x0 0x7081e000 0x0 0x1000 0x0 0x7081f000 0x0 0x1000 0x0 0x70801000 0x0 0x1000 0x0 0x70803000 0x0 0x1000 0x0 0x70804000 0x0 0x1000>; | |
| }; | |
| dtv@7000c300 { | |
| compatible = "nvidia,tegra124-dtv"; | |
| reg = <0x0 0x7000c300 0x0 0x100>; | |
| nvidia,dma-request-selector = <0xb>; | |
| dmas = <0xb 0xb>; | |
| dma-names = "rx"; | |
| status = "okay"; | |
| }; | |
| snor { | |
| compatible = "nvidia,tegra124-nor"; | |
| reg = <0x0 0x70009000 0x0 0x1000>; | |
| interrupts = <0x0 0x60 0x4>; | |
| status = "disabled"; | |
| }; | |
| gpu_edp { | |
| compatible = "nvidia,tegra124-gpu-edp-capping"; | |
| nvidia,freq_step = <0xb71b00>; | |
| nvidia,edp_clk = "gbus"; | |
| nvidia,edp_cap_clk = "edp.gbus"; | |
| nvidia,tegra-ppm-cdyn = <0xa271f0>; | |
| nvidia,tegra-ppm-min_leakage = <0x1e>; | |
| nvidia,tegra-ppm-leakage_coeffs = <0xf38e0388 0x23ff61a 0xff6cc51b 0xb129c 0x29fd00d3 0xf8063e69 0x20df887 0xffda6672 0xd149a96f 0x8bc49d1 0xfdb2a8d0 0x28803d 0x117264cc 0xfcf20909 0xd562f3 0xfff1bbcc 0x6dc372f 0xfc16fbca 0xabb0b8 0xfff33506 0xe8788877 0xfae8366 0xfd1436fa 0x32c13d 0x1a52f3f4 0xed531c6e 0x3ac205e 0xffc43c0e 0xf6393ace 0x712374d 0xfe8b971b 0x172805 0xfdaf13e0 0xbad354 0xffe20781 0x2c3f0 0x88a0d36 0xfbc2efd9 0xd56790 0xfff1fe45 0xf5c7c7ee 0x5e53002 0xfebb9529 0x128e9f 0x40503e0 0xfd95b684 0x8d606b 0xfff89a2e 0x1b6764 0xfffaba41 0x1443c 0xffffb1d9 0xff7d8d0f 0x60a333 0xffe96b79 0x1c2f1 0xba0b22 0xff59f91b 0x282a14 0xfffd8984 0xffaeb135 0x4b969c 0xffed75c2 0xfc2c>; | |
| }; | |
| soctherm@0x700E2000 { | |
| compatible = "nvidia,tegra-soctherm"; | |
| reg = <0x0 0x700e2000 0x0 0x600 0x0 0x60006000 0x0 0x400 0x0 0x70040000 0x0 0x200>; | |
| interrupts = <0x0 0x30 0x4 0x0 0x33 0x4>; | |
| #thermal-sensor-cells = <0x1>; | |
| status = "okay"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| soctherm-clock-frequency = <0x30a32c0>; | |
| tsensor-clock-frequency = <0x61a80>; | |
| sensor-params-tall = <0x3fac>; | |
| sensor-params-tiddq = <0x1>; | |
| sensor-params-ten-count = <0x1>; | |
| sensor-params-tsample = <0x78>; | |
| sensor-params-pdiv = <0x8>; | |
| sensor-params-tsamp-ate = <0x1e0>; | |
| sensor-params-pdiv-ate = <0x8>; | |
| therm_cpu { | |
| device_type = "thermctl"; | |
| thermal-sensor-id = <0x0>; | |
| hotspot-offset = <0x2710>; | |
| }; | |
| therm_gpu { | |
| device_type = "thermctl"; | |
| thermal-sensor-id = <0x1>; | |
| hotspot-offset = <0x1388>; | |
| }; | |
| therm_mem { | |
| device_type = "thermctl"; | |
| thermal-sensor-id = <0x2>; | |
| }; | |
| therm_pll { | |
| device_type = "thermctl"; | |
| thermal-sensor-id = <0x3>; | |
| }; | |
| throttle@critical { | |
| device_type = "throttlectl"; | |
| cdev-type = "tegra-shutdown"; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x3>; | |
| #cooling-cells = <0x2>; | |
| }; | |
| throttle@heavy { | |
| device_type = "throttlectl"; | |
| cdev-type = "tegra-heavy"; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x3>; | |
| #cooling-cells = <0x2>; | |
| priority = <0x64>; | |
| throttle_dev = <0xf 0x10>; | |
| }; | |
| throttle@light { | |
| device_type = "throttlectl"; | |
| cdev-type = "tegra-light"; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x3>; | |
| #cooling-cells = <0x2>; | |
| priority = <0x32>; | |
| throttle_dev = <0x11 0x12>; | |
| }; | |
| throttle@oc1 { | |
| device_type = "throttlectl"; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x3>; | |
| #cooling-cells = <0x2>; | |
| priority = <0xa>; | |
| throttle_dev = <0x13 0x14>; | |
| }; | |
| throttle@oc2 { | |
| device_type = "throttlectl"; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x3>; | |
| #cooling-cells = <0x2>; | |
| priority = <0xa>; | |
| throttle_dev = <0x13 0x14>; | |
| }; | |
| throttle@oc3 { | |
| device_type = "throttlectl"; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x3>; | |
| #cooling-cells = <0x2>; | |
| priority = <0xa>; | |
| throttle_dev = <0x13 0x14>; | |
| }; | |
| throttle@oc4 { | |
| device_type = "throttlectl"; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x3>; | |
| #cooling-cells = <0x2>; | |
| priority = <0xa>; | |
| throttle_dev = <0x13 0x14>; | |
| }; | |
| throttle_dev@cpu_low { | |
| device_type = "throttle_dev"; | |
| depth = <0x32>; | |
| linux,phandle = <0x11>; | |
| phandle = <0x11>; | |
| }; | |
| throttle_dev@cpu_medium { | |
| device_type = "throttle_dev"; | |
| depth = <0x4b>; | |
| linux,phandle = <0x13>; | |
| phandle = <0x13>; | |
| }; | |
| throttle_dev@cpu_high { | |
| device_type = "throttle_dev"; | |
| depth = <0x50>; | |
| linux,phandle = <0xf>; | |
| phandle = <0xf>; | |
| }; | |
| throttle_dev@gpu_low { | |
| device_type = "throttle_dev"; | |
| depth = <0x32>; | |
| linux,phandle = <0x12>; | |
| phandle = <0x12>; | |
| }; | |
| throttle_dev@gpu_medium { | |
| device_type = "throttle_dev"; | |
| depth = <0x4b>; | |
| linux,phandle = <0x14>; | |
| phandle = <0x14>; | |
| }; | |
| throttle_dev@gpu_high { | |
| device_type = "throttle_dev"; | |
| depth = <0x50>; | |
| linux,phandle = <0x10>; | |
| phandle = <0x10>; | |
| }; | |
| }; | |
| bthrot_cdev { | |
| compatible = "nvidia,balanced-throttle"; | |
| skin_balanced { | |
| cdev-type = "skin-balanced"; | |
| num_states = <0x14>; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x14>; | |
| #cooling-cells = <0x2>; | |
| status = "okay"; | |
| throttle_table = <0x1e8480 0xc44a0 0x75300 0xb8920 0x5dc00 0xe1960 0x1cfde0 0xb8920 0x75300 0x9e340 0x5dc00 0xe1960 0x1b7740 0xacda0 0x6c660 0x9e340 0x5dc00 0xe1960 0x19f0a0 0x9e340 0x6c660 0x927c0 0x493e0 0xe1960 0x186a00 0x9e340 0x6c660 0x927c0 0x493e0 0xe1960 0x16e360 0x956a0 0x6c660 0x927c0 0x493e0 0xe1960 0x162010 0x956a0 0x6c660 0x927c0 0x493e0 0xe1960 0x155cc0 0x83d60 0x6c660 0x927c0 0x493e0 0xe1960 0x149970 0x83d60 0x6c660 0x927c0 0x493e0 0xe1960 0x13d620 0x83d60 0x6c660 0x927c0 0x493e0 0xe1960 0x1312d0 0x72420 0x6c660 0x927c0 0x493e0 0xe1960 0x124f80 0x72420 0x60ae0 0x927c0 0x493e0 0xe1960 0x118c30 0x72420 0x60ae0 0x927c0 0x31ce0 0xe1960 0x10c8e0 0x72420 0x60ae0 0x927c0 0x31ce0 0xe1960 0x100590 0x60ae0 0x60ae0 0x7b0c0 0x31ce0 0xe1960 0xf4240 0x60ae0 0x60ae0 0x7b0c0 0x31ce0 0xe1960 0xee098 0x60ae0 0x60ae0 0x7b0c0 0x31ce0 0xc15c0 0xe7ef0 0x60ae0 0x54f60 0x7b0c0 0x21340 0xc15c0 0xe1d48 0x60ae0 0x54f60 0x7b0c0 0x21340 0xc15c0 0xdbba0 0x60ae0 0x54f60 0x668a0 0x21340 0xc15c0 0xd59f8 0x60ae0 0x43620 0x668a0 0x21340 0x927c0 0xcf850 0x60ae0 0x54f60 0x668a0 0x21340 0x927c0 0xc96a8 0x60ae0 0x54f60 0x668a0 0x21340 0x927c0 0xc3500 0x60ae0 0x54f60 0x668a0 0x21340 0x927c0 0xbd358 0x60ae0 0x54f60 0x52080 0x18e70 0x80e80 0xb71b0 0x4f1a0 0x43620 0x52080 0x18e70 0x80e80 0xb1008 0x4f1a0 0x43620 0x52080 0x13ec0 0x80e80 0xaae60 0x4f1a0 0x43620 0x52080 0x13ec0 0x80e80 0xa4cb8 0x4f1a0 0x43620 0x52080 0x13ec0 0x60ae0 0x9eb10 0x4f1a0 0x43620 0x52080 0x13ec0 0x60ae0 0x98968 0x4f1a0 0x43620 0x52080 0x13ec0 0x60ae0 0x927c0 0x3d860 0x43620 0x52080 0x13ec0 0x60ae0 0x8c618 0x3d860 0x43620 0x52080 0x13ec0 0x60ae0 0x86470 0x3d860 0x43620 0x52080 0x13ec0 0x493e0>; | |
| linux,phandle = <0x8>; | |
| phandle = <0x8>; | |
| }; | |
| gpu_balanced { | |
| cdev-type = "gpu-balanced"; | |
| num_states = <0x53>; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x53>; | |
| #cooling-cells = <0x2>; | |
| status = "okay"; | |
| throttle_table = <0x2304d8 0xbf1d0 0x75300 0xb8920 0x5dc00 0xe1960 0x22a13c 0xbc868 0x75300 0xb8920 0x5dc00 0xe1960 0x223da0 0xb9f00 0x75300 0xb8920 0x5dc00 0xe1960 0x21da04 0xb75fc 0x75300 0xb8920 0x5dc00 0xe1960 0x217668 0xb4c94 0x75300 0xb8920 0x5dc00 0xe1960 0x2112cc 0xb232c 0x75300 0xb8920 0x5dc00 0xe1960 0x20af30 0xaf9c4 0x75300 0xb8920 0x5dc00 0xe1960 0x204b94 0xad05c 0x75300 0xb8920 0x5dc00 0xe1960 0x1fe7f8 0xaa6f4 0x75300 0xb8920 0x5dc00 0xe1960 0x1f845c 0xa7d8c 0x75300 0xb8920 0x5dc00 0xe1960 0x1f20c0 0xa5424 0x75300 0xb8920 0x5dc00 0xe1960 0x1ebd24 0xa2990 0x75300 0xb8920 0x5dc00 0xe1960 0x1e5988 0xa0280 0x75300 0xb8920 0x5dc00 0xe1960 0x1df5ec 0x9d788 0x75300 0xb8920 0x5dc00 0xe1960 0x1d9250 0x9b078 0x75300 0xb8920 0x5dc00 0xe1960 0x1d2eb4 0x98580 0x75300 0xb8920 0x5dc00 0xe1960 0x1ccb18 0x95a88 0x75300 0xb8920 0x5dc00 0xe1960 0x1c677c 0x93378 0x75300 0xb8920 0x5dc00 0xe1960 0x1c03e0 0x90880 0x75300 0xb8920 0x5dc00 0xe1960 0x1ba044 0x8e170 0x75300 0xb8920 0x5dc00 0xe1960 0x1b3ca8 0x8b678 0x75300 0xb8920 0x5dc00 0xe1960 0x1ad90c 0x88b80 0x75300 0xb8920 0x5dc00 0xe1960 0x1a7570 0x86470 0x75300 0xb8920 0x5dc00 0xe1960 0x1a11d4 0x83978 0x75300 0xb8920 0x5dc00 0xe1960 0x19ae38 0x81268 0x75300 0xb8920 0x5dc00 0xe1960 0x194a9c 0x7e770 0x75300 0xb8920 0x5dc00 0xe1960 0x18e700 0x7c060 0x75300 0xb8920 0x5dc00 0xe1960 0x188364 0x79568 0x75300 0xb8920 0x5dc00 0xe1960 0x181fc8 0x76a70 0x75300 0xb8920 0x5dc00 0xe1960 0x17bc2c 0x74360 0x75300 0xb8920 0x5dc00 0xe1960 0x175890 0x71868 0x75300 0xb8920 0x5dc00 0xe1960 0x16f4f4 0x6f158 0x75300 0xb8920 0x5dc00 0xe1960 0x169158 0x6c660 0x75300 0xb8920 0x5dc00 0xe1960 0x162dbc 0x69b68 0x75300 0xb8920 0x5dc00 0xe1960 0x15ca20 0x67458 0x75300 0xb8920 0x5dc00 0xe1960 0x156684 0x64960 0x75300 0xb8920 0x5dc00 0xe1960 0x1502e8 0x62250 0x75300 0xb8920 0x5dc00 0xe1960 0x149f4c 0x5f758 0x75300 0xb8920 0x5dc00 0xe1960 0x143bb0 0x5cc60 0x75300 0xb8920 0x5dc00 0xe1960 0x13d814 0x5a550 0x75300 0xb8920 0x5dc00 0xe1960 0x137478 0x57a58 0x75300 0xb8920 0x5dc00 0xe1960 0x1310dc 0x55348 0x75300 0xb8920 0x5dc00 0xe1960 0x12ad40 0x52850 0x75300 0xb8920 0x5dc00 0xc15c0 0x1249a4 0x50140 0x75300 0xb8920 0x5dc00 0xc15c0 0x11e608 0x4d648 0x75300 0xb8920 0x57e40 0xc15c0 0x11826c 0x4ab50 0x75300 0xb8920 0x57e40 0xc15c0 0x111ed0 0x48440 0x75300 0xa6fe0 0x57e40 0xc15c0 0x10bb34 0x45948 0x6c660 0xa6fe0 0x57e40 0xc15c0 0x105798 0x43238 0x6c660 0xa6fe0 0x57e40 0xc15c0 0xff3fc 0x40740 0x6c660 0xa6fe0 0x57e40 0xc15c0 0xf9060 0x3dc48 0x6c660 0xa6fe0 0x4f1a0 0xc15c0 0xf2cc4 0x3b538 0x6c660 0xa6fe0 0x4f1a0 0xc15c0 0xec928 0x38a40 0x6c660 0x927c0 0x4f1a0 0xc15c0 0xe658c 0x36330 0x6c660 0x927c0 0x4f1a0 0xc15c0 0xe01f0 0x33838 0x60ae0 0x927c0 0x4f1a0 0xc15c0 0xd9e54 0x30d40 0x60ae0 0x927c0 0x4f1a0 0xc15c0 0xd3ab8 0x2e630 0x60ae0 0x927c0 0x4f1a0 0xc15c0 0xcd71c 0x2bb38 0x60ae0 0x927c0 0x46500 0xc15c0 0xc7380 0x29428 0x60ae0 0x927c0 0x46500 0xc15c0 0xc0fe4 0x26930 0x60ae0 0x927c0 0x46500 0xc15c0 0xbac48 0x24220 0x60ae0 0x7b0c0 0x46500 0xc15c0 0xb48ac 0x21728 0x54f60 0x7b0c0 0x46500 0xc15c0 0xae510 0x1ec30 0x54f60 0x7b0c0 0x46500 0x98580 0xa8174 0x1c520 0x54f60 0x7b0c0 0x46500 0x98580 0xa1dd8 0x19a28 0x54f60 0x7b0c0 0x46500 0x98580 0x9ba3c 0x17318 0x54f60 0x7b0c0 0x46500 0x98580 0x956a0 0x14820 0x54f60 0x7b0c0 0x3d860 0x98580 0x8f304 0x14820 0x54f60 0x7b0c0 0x3d860 0x98580 0x88f68 0x14820 0x54f60 0x668a0 0x3d860 0x98580 0x82bcc 0x14820 0x46500 0x668a0 0x3d860 0x98580 0x7c830 0x14820 0x46500 0x668a0 0x3d860 0x98580 0x76494 0x14820 0x46500 0x668a0 0x3d860 0x98580 0x700f8 0x14820 0x46500 0x668a0 0x3d860 0x98580 0x69d5c 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x639c0 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x5d624 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x57288 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x50eec 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x4ab50 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x447b4 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x3e418 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x3807c 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x31ce0 0x14820 0x46500 0x668a0 0x3d860 0x60ae0>; | |
| }; | |
| cpu_balanced { | |
| cdev-type = "cpu-balanced"; | |
| num_states = <0x53>; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x53>; | |
| #cooling-cells = <0x2>; | |
| status = "okay"; | |
| throttle_table = <0x2304d8 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x22a13c 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x223da0 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x21da04 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x217668 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x2112cc 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x20af30 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x204b94 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1fe7f8 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1f845c 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1f20c0 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1ebd24 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1e5988 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1df5ec 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1d9250 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1d2eb4 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1ccb18 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1c677c 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1c03e0 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1ba044 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1b3ca8 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1ad90c 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1a7570 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1a11d4 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x19ae38 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x194a9c 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x18e700 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x188364 0xc0df0 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x181fc8 0xbd740 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x17bc2c 0xba090 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x175890 0xb6dc8 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x16f4f4 0xb3718 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x169158 0xb0068 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x162dbc 0xac9b8 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x15ca20 0xa9308 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x156684 0xa5c58 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1502e8 0xa2990 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x149f4c 0x9f2e0 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x143bb0 0x9bc30 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x13d814 0x98580 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x137478 0x94ed0 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x1310dc 0x91820 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x12ad40 0x8e170 0xffffffff 0xffffffff 0xffffffff 0xc15c0 0x1249a4 0x8aea8 0xffffffff 0xffffffff 0xffffffff 0xc15c0 0x11e608 0x877f8 0xffffffff 0xffffffff 0x57e40 0xc15c0 0x11826c 0x84148 0xffffffff 0xffffffff 0x57e40 0xc15c0 0x111ed0 0x80a98 0xffffffff 0xa6fe0 0x57e40 0xc15c0 0x10bb34 0x7d3e8 0x6c660 0xa6fe0 0x57e40 0xc15c0 0x105798 0x79d38 0x6c660 0xa6fe0 0x57e40 0xc15c0 0xff3fc 0x76a70 0x6c660 0xa6fe0 0x57e40 0xc15c0 0xf9060 0x733c0 0x6c660 0xa6fe0 0x4f1a0 0xc15c0 0xf2cc4 0x6fd10 0x6c660 0xa6fe0 0x4f1a0 0xc15c0 0xec928 0x6c660 0x6c660 0x927c0 0x4f1a0 0xc15c0 0xe658c 0x68fb0 0x6c660 0x927c0 0x4f1a0 0xc15c0 0xe01f0 0x65900 0x60ae0 0x927c0 0x4f1a0 0xc15c0 0xd9e54 0x62250 0x60ae0 0x927c0 0x4f1a0 0xc15c0 0xd3ab8 0x5ef88 0x60ae0 0x927c0 0x4f1a0 0xc15c0 0xcd71c 0x5b8d8 0x60ae0 0x927c0 0x46500 0xc15c0 0xc7380 0x58228 0x60ae0 0x927c0 0x46500 0xc15c0 0xc0fe4 0x54b78 0x60ae0 0x927c0 0x46500 0xc15c0 0xbac48 0x514c8 0x60ae0 0x7b0c0 0x46500 0xc15c0 0xb48ac 0x4de18 0x54f60 0x7b0c0 0x46500 0xc15c0 0xae510 0x4ab50 0x54f60 0x7b0c0 0x46500 0x98580 0xa8174 0x474a0 0x54f60 0x7b0c0 0x46500 0x98580 0xa1dd8 0x43df0 0x54f60 0x7b0c0 0x46500 0x98580 0x9ba3c 0x40740 0x54f60 0x7b0c0 0x46500 0x98580 0x956a0 0x3d090 0x54f60 0x7b0c0 0x3d860 0x98580 0x8f304 0x399e0 0x54f60 0x7b0c0 0x3d860 0x98580 0x88f68 0x36330 0x54f60 0x668a0 0x3d860 0x98580 0x82bcc 0x33068 0x46500 0x668a0 0x3d860 0x98580 0x7c830 0x2f9b8 0x46500 0x668a0 0x3d860 0x98580 0x76494 0x2c308 0x46500 0x668a0 0x3d860 0x98580 0x700f8 0x28c58 0x46500 0x668a0 0x3d860 0x98580 0x69d5c 0x255a8 0x46500 0x668a0 0x3d860 0x60ae0 0x639c0 0x21ef8 0x46500 0x668a0 0x3d860 0x60ae0 0x5d624 0x1ec30 0x46500 0x668a0 0x3d860 0x60ae0 0x57288 0x1b580 0x46500 0x668a0 0x3d860 0x60ae0 0x50eec 0x17ed0 0x46500 0x668a0 0x3d860 0x60ae0 0x4ab50 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x447b4 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x3e418 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x3807c 0x14820 0x46500 0x668a0 0x3d860 0x60ae0 0x31ce0 0x14820 0x46500 0x668a0 0x3d860 0x60ae0>; | |
| }; | |
| emergency_balanced { | |
| cdev-type = "emergency-balanced"; | |
| num_states = <0x1>; | |
| cooling-min-state = <0x0>; | |
| cooling-max-state = <0x1>; | |
| #cooling-cells = <0x2>; | |
| status = "okay"; | |
| throttle_table = <0x111ed0 0x5f758 0x46500 0x668a0 0x3d860 0x60ae0>; | |
| }; | |
| }; | |
| chosen { | |
| bootargs = "tegraid=40.0.0.00.00 console=tty1 gpt fbcon=rotate:2 earlyprintk clk_ignore_unused"; | |
| linux,initrd-start = <0x81680000>; | |
| linux,initrd-end = <0x82800000>; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x0 0x80000000 0x0 0x2d000000 0x0 0xae000000 0x0 0x30000000>; | |
| }; | |
| pcie-controller@01003000 { | |
| compatible = "nvidia,tegra124-pcie"; | |
| device_type = "pci"; | |
| reg = <0x0 0x1003000 0x0 0x800 0x0 0x1003800 0x0 0x800 0x0 0x2000000 0x0 0x10000000>; | |
| reg-names = "pads", "afi", "cs"; | |
| interrupts = <0x0 0x62 0x4 0x0 0x63 0x4>; | |
| interrupt-names = "intr", "msi"; | |
| #interrupt-cells = <0x1>; | |
| interrupt-map-mask = <0x0 0x0 0x0 0x0>; | |
| interrupt-map = <0x0 0x0 0x0 0x0 0x1 0x0 0x62 0x4>; | |
| bus-range = <0x0 0xff>; | |
| #address-cells = <0x3>; | |
| #size-cells = <0x2>; | |
| ranges = <0x82000000 0x0 0x1000000 0x0 0x1000000 0x0 0x1000 0x82000000 0x0 0x1001000 0x0 0x1001000 0x0 0x1000 0x81000000 0x0 0x0 0x0 0x12000000 0x0 0x10000 0x82000000 0x0 0x13000000 0x0 0x13000000 0x0 0xd000000 0xc2000000 0x0 0x20000000 0x0 0x20000000 0x0 0x20000000>; | |
| clocks = <0x2 0x46 0x2 0x48 0x2 0xe7 0x2 0x10c>; | |
| clock-names = "pex", "afi", "pll_e", "cml"; | |
| resets = <0x2 0x46 0x2 0x48 0x2 0x4a>; | |
| reset-names = "pex", "afi", "pcie_x"; | |
| status = "disabled"; | |
| phys = <0xe 0x0>; | |
| phy-names = "pcie"; | |
| pci@1,0 { | |
| device_type = "pci"; | |
| assigned-addresses = <0x82000800 0x0 0x1000000 0x0 0x1000>; | |
| reg = <0x800 0x0 0x0 0x0 0x0>; | |
| status = "disabled"; | |
| #address-cells = <0x3>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| nvidia,num-lanes = <0x2>; | |
| }; | |
| pci@2,0 { | |
| device_type = "pci"; | |
| assigned-addresses = <0x82001000 0x0 0x1001000 0x0 0x1000>; | |
| reg = <0x1000 0x0 0x0 0x0 0x0>; | |
| status = "disabled"; | |
| #address-cells = <0x3>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| nvidia,num-lanes = <0x1>; | |
| }; | |
| }; | |
| interrupt-controller@50041000 { | |
| compatible = "arm,cortex-a15-gic"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x3>; | |
| reg = <0x0 0x50041000 0x0 0x1000 0x0 0x50042000 0x0 0x1000 0x0 0x50044000 0x0 0x2000 0x0 0x50046000 0x0 0x2000>; | |
| interrupts = <0x1 0x9 0xf04>; | |
| interrupt-parent = <0x1>; | |
| linux,phandle = <0x1>; | |
| phandle = <0x1>; | |
| }; | |
| gpu@57000000 { | |
| compatible = "nvidia,gk20a"; | |
| reg = <0x0 0x57000000 0x0 0x1000000 0x0 0x58000000 0x0 0x1000000>; | |
| interrupts = <0x0 0x9d 0x4 0x0 0x9e 0x4>; | |
| interrupt-names = "stall", "nonstall"; | |
| clocks = <0x2 0xb8 0x2 0x10b>; | |
| clock-names = "gpu", "pwr"; | |
| resets = <0x2 0xb8>; | |
| reset-names = "gpu"; | |
| iommus = <0x4 0x13>; | |
| status = "disabled"; | |
| }; | |
| interrupt-controller@60004000 { | |
| compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; | |
| reg = <0x0 0x60004000 0x0 0x100 0x0 0x60004100 0x0 0x100 0x0 0x60004200 0x0 0x100 0x0 0x60004300 0x0 0x100 0x0 0x60004400 0x0 0x100>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x3>; | |
| num-ictrls = <0x5>; | |
| interrupt-parent = <0x1>; | |
| }; | |
| watchdog@60005100 { | |
| compatible = "nvidia,tegra-wdt"; | |
| reg = <0x0 0x60005100 0x0 0x20 0x0 0x60005070 0x0 0x8>; | |
| }; | |
| clock@60006000 { | |
| compatible = "nvidia,tegra124-car"; | |
| reg = <0x0 0x60006000 0x0 0x1000>; | |
| #clock-cells = <0x1>; | |
| #reset-cells = <0x1>; | |
| nvidia,external-memory-controller = <0x15>; | |
| linux,phandle = <0x2>; | |
| phandle = <0x2>; | |
| }; | |
| flow-controller@60007000 { | |
| compatible = "nvidia,tegra124-flowctrl"; | |
| reg = <0x0 0x60007000 0x0 0x1000>; | |
| }; | |
| actmon@6000c800 { | |
| compatible = "nvidia,tegra124-actmon"; | |
| reg = <0x0 0x6000c800 0x0 0x400>; | |
| interrupts = <0x0 0x2d 0x4>; | |
| clocks = <0x2 0x77 0x2 0x39>; | |
| clock-names = "actmon", "emc"; | |
| resets = <0x2 0x77>; | |
| reset-names = "actmon"; | |
| }; | |
| apbmisc@70000800 { | |
| compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; | |
| reg = <0x0 0x70000800 0x0 0x64 0x0 0x7000e864 0x0 0x4>; | |
| }; | |
| rtc@7000e000 { | |
| compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; | |
| reg = <0x0 0x7000e000 0x0 0x100>; | |
| interrupts = <0x0 0x2 0x4>; | |
| clocks = <0x2 0x4>; | |
| }; | |
| fuse@7000f800 { | |
| compatible = "nvidia,tegra124-efuse"; | |
| reg = <0x0 0x7000f800 0x0 0x400>; | |
| clocks = <0x2 0xc6>; | |
| clock-names = "fuse"; | |
| resets = <0x2 0x27>; | |
| reset-names = "fuse"; | |
| }; | |
| emc@7001b000 { | |
| compatible = "nvidia,tegra124-emc"; | |
| reg = <0x0 0x7001b000 0x0 0x1000>; | |
| nvidia,memory-controller = <0x4>; | |
| linux,phandle = <0x15>; | |
| phandle = <0x15>; | |
| }; | |
| padctl@7009f000 { | |
| compatible = "nvidia,tegra124-xusb-padctl"; | |
| reg = <0x0 0x7009f000 0x0 0x1000>; | |
| resets = <0x2 0x8e>; | |
| reset-names = "padctl"; | |
| #phy-cells = <0x1>; | |
| linux,phandle = <0xe>; | |
| phandle = <0xe>; | |
| }; | |
| thermal-sensor@700e2000 { | |
| compatible = "nvidia,tegra124-soctherm"; | |
| reg = <0x0 0x700e2000 0x0 0x1000>; | |
| interrupts = <0x0 0x30 0x4>; | |
| clocks = <0x2 0x64 0x2 0x4e>; | |
| clock-names = "tsensor", "soctherm"; | |
| resets = <0x2 0x4e>; | |
| reset-names = "soctherm"; | |
| #thermal-sensor-cells = <0x1>; | |
| linux,phandle = <0x9>; | |
| phandle = <0x9>; | |
| fuse_war@fuse_rev_new { | |
| device_type = "fuse_war"; | |
| match_fuse_rev = <0x0>; | |
| cpu0 = <0x115328 0xffa05fec>; | |
| cpu1 = <0x111fac 0xffa903a4>; | |
| cpu2 = <0x113258 0xff98b9b8>; | |
| cpu3 = <0x10f374 0xffa0e840>; | |
| mem0 = <0x111ffc 0xffa56af0>; | |
| mem1 = <0x117b64 0xff934988>; | |
| gpu = <0x111764 0xffa4708c>; | |
| pllx = <0x10e244 0xff9951ac>; | |
| }; | |
| fuse_war@fuse_rev_old { | |
| device_type = "fuse_war"; | |
| match_fuse_rev = <0x1>; | |
| cpu0 = <0x11858c 0xff9bb6f4>; | |
| cpu1 = <0x112ed4 0xffa794d8>; | |
| cpu2 = <0x11a2d8 0xff8e2070>; | |
| cpu3 = <0x115134 0xff981350>; | |
| mem0 = <0x10372c 0xffbbe5a0>; | |
| mem1 = <0x108d1c 0xffaa7fb8>; | |
| gpu = <0x108b8c 0xffb1ffa4>; | |
| pllx = <0x114fa4 0xff8eebf4>; | |
| }; | |
| }; | |
| clock@70110000 { | |
| compatible = "nvidia,tegra124-dfll"; | |
| reg = <0x0 0x70110000 0x0 0x100 0x0 0x70110000 0x0 0x100 0x0 0x70110100 0x0 0x100 0x0 0x70110200 0x0 0x100>; | |
| interrupts = <0x0 0x3e 0x4>; | |
| clocks = <0x2 0x109 0x2 0x108 0x2 0x2f>; | |
| clock-names = "soc", "ref", "i2c"; | |
| resets = <0x2 0xc0>; | |
| reset-names = "dvco"; | |
| #clock-cells = <0x0>; | |
| clock-output-names = "dfllCPU_out"; | |
| nvidia,sample-rate = <0x30d4>; | |
| nvidia,droop-ctrl = <0xf00>; | |
| nvidia,force-mode = <0x1>; | |
| nvidia,cf = <0xa>; | |
| nvidia,ci = <0x0>; | |
| nvidia,cg = <0x2>; | |
| status = "disabled"; | |
| linux,phandle = <0x19>; | |
| phandle = <0x19>; | |
| }; | |
| usb@7d000000 { | |
| compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; | |
| reg = <0x0 0x7d000000 0x0 0x4000>; | |
| interrupts = <0x0 0x14 0x4>; | |
| phy_type = "utmi"; | |
| clocks = <0x2 0x16>; | |
| resets = <0x2 0x16>; | |
| reset-names = "usb"; | |
| nvidia,phy = <0x16>; | |
| status = "disabled"; | |
| }; | |
| usb-phy@7d000000 { | |
| compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; | |
| reg = <0x0 0x7d000000 0x0 0x4000 0x0 0x7d000000 0x0 0x4000>; | |
| phy_type = "utmi"; | |
| clocks = <0x2 0x16 0x2 0xde 0x2 0x16>; | |
| clock-names = "reg", "pll_u", "utmi-pads"; | |
| resets = <0x2 0x16 0x2 0x16>; | |
| reset-names = "usb", "utmi-pads"; | |
| nvidia,hssync-start-delay = <0x0>; | |
| nvidia,idle-wait-delay = <0x11>; | |
| nvidia,elastic-limit = <0x10>; | |
| nvidia,term-range-adj = <0x6>; | |
| nvidia,xcvr-setup = <0x9>; | |
| nvidia,xcvr-lsfslew = <0x0>; | |
| nvidia,xcvr-lsrslew = <0x3>; | |
| nvidia,hssquelch-level = <0x2>; | |
| nvidia,hsdiscon-level = <0x5>; | |
| nvidia,xcvr-hsslew = <0xc>; | |
| nvidia,has-utmi-pad-registers; | |
| status = "disabled"; | |
| linux,phandle = <0x16>; | |
| phandle = <0x16>; | |
| }; | |
| usb@7d004000 { | |
| compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; | |
| reg = <0x0 0x7d004000 0x0 0x4000>; | |
| interrupts = <0x0 0x15 0x4>; | |
| phy_type = "utmi"; | |
| clocks = <0x2 0x3a>; | |
| resets = <0x2 0x3a>; | |
| reset-names = "usb"; | |
| nvidia,phy = <0x17>; | |
| status = "disabled"; | |
| }; | |
| usb-phy@7d004000 { | |
| compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; | |
| reg = <0x0 0x7d004000 0x0 0x4000 0x0 0x7d000000 0x0 0x4000>; | |
| phy_type = "utmi"; | |
| clocks = <0x2 0x3a 0x2 0xde 0x2 0x16>; | |
| clock-names = "reg", "pll_u", "utmi-pads"; | |
| resets = <0x2 0x3a 0x2 0x16>; | |
| reset-names = "usb", "utmi-pads"; | |
| nvidia,hssync-start-delay = <0x0>; | |
| nvidia,idle-wait-delay = <0x11>; | |
| nvidia,elastic-limit = <0x10>; | |
| nvidia,term-range-adj = <0x6>; | |
| nvidia,xcvr-setup = <0x9>; | |
| nvidia,xcvr-lsfslew = <0x0>; | |
| nvidia,xcvr-lsrslew = <0x3>; | |
| nvidia,hssquelch-level = <0x2>; | |
| nvidia,hsdiscon-level = <0x5>; | |
| nvidia,xcvr-hsslew = <0xc>; | |
| status = "disabled"; | |
| linux,phandle = <0x17>; | |
| phandle = <0x17>; | |
| }; | |
| usb@7d008000 { | |
| compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; | |
| reg = <0x0 0x7d008000 0x0 0x4000>; | |
| interrupts = <0x0 0x61 0x4>; | |
| phy_type = "utmi"; | |
| clocks = <0x2 0x3b>; | |
| resets = <0x2 0x3b>; | |
| reset-names = "usb"; | |
| nvidia,phy = <0x18>; | |
| status = "disabled"; | |
| }; | |
| usb-phy@7d008000 { | |
| compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; | |
| reg = <0x0 0x7d008000 0x0 0x4000 0x0 0x7d000000 0x0 0x4000>; | |
| phy_type = "utmi"; | |
| clocks = <0x2 0x3b 0x2 0xde 0x2 0x16>; | |
| clock-names = "reg", "pll_u", "utmi-pads"; | |
| resets = <0x2 0x3b 0x2 0x16>; | |
| reset-names = "usb", "utmi-pads"; | |
| nvidia,hssync-start-delay = <0x0>; | |
| nvidia,idle-wait-delay = <0x11>; | |
| nvidia,elastic-limit = <0x10>; | |
| nvidia,term-range-adj = <0x6>; | |
| nvidia,xcvr-setup = <0x9>; | |
| nvidia,xcvr-lsfslew = <0x0>; | |
| nvidia,xcvr-lsrslew = <0x3>; | |
| nvidia,hssquelch-level = <0x2>; | |
| nvidia,hsdiscon-level = <0x5>; | |
| nvidia,xcvr-hsslew = <0xc>; | |
| status = "disabled"; | |
| linux,phandle = <0x18>; | |
| phandle = <0x18>; | |
| }; | |
| cpus { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a15"; | |
| reg = <0x0>; | |
| clocks = <0x2 0x106 0x2 0x107 0x2 0xe3 0x2 0xd3 0x19>; | |
| clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; | |
| clock-latency = <0x493e0>; | |
| linux,phandle = <0x1a>; | |
| phandle = <0x1a>; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a15"; | |
| reg = <0x1>; | |
| linux,phandle = <0x1b>; | |
| phandle = <0x1b>; | |
| }; | |
| cpu@2 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a15"; | |
| reg = <0x2>; | |
| linux,phandle = <0x1c>; | |
| phandle = <0x1c>; | |
| }; | |
| cpu@3 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a15"; | |
| reg = <0x3>; | |
| linux,phandle = <0x1d>; | |
| phandle = <0x1d>; | |
| }; | |
| }; | |
| pmu { | |
| compatible = "arm,cortex-a15-pmu"; | |
| interrupts = <0x0 0x90 0x4 0x0 0x91 0x4 0x0 0x92 0x4 0x0 0x93 0x4>; | |
| interrupt-affinity = <0x1a 0x1b 0x1c 0x1d>; | |
| }; | |
| timer { | |
| compatible = "arm,armv7-timer"; | |
| interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>; | |
| interrupt-parent = <0x1>; | |
| }; | |
| framebuffer { | |
| compatible = "simple-framebuffer"; | |
| reg = <0x0 0xad012000 0x0 0x8e8000>; | |
| width = <0x4b0>; | |
| height = <0x780>; | |
| stride = <0x1300>; | |
| format = "a8b8g8r8"; | |
| }; | |
| }; |
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