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StratixV second PCIe HIP

Short walkthrough on how to enable second, hidden PCIe HIP on 5SGSMD5K1F40C1 (5SGSKF40I3LNAC)

  1. Create a file named preload_me.c with following content:
#include <stdio.h>
#include <dlfcn.h>
#include <stdlib.h>
#include <string.h>
#include <stdbool.h>

void *lib_ptr = NULL;
bool (*is_global_id_enabled_next)(void *db, unsigned id);

void do_init() {
	if (lib_ptr != NULL)
	lib_ptr = dlopen("", RTLD_LOCAL | RTLD_LAZY);
	if (lib_ptr == NULL) {
		fprintf(stderr, "failed to open\n");
	is_global_id_enabled_next = dlsym(lib_ptr, "_ZNK12DEV_DIE_INFO20is_global_id_enabledEj");
	if (is_global_id_enabled_next == NULL) {
		fprintf(stderr, "failed to dlsym _ZNK12DEV_DIE_INFO20is_global_id_enabledEj\n");

bool _ZNK12DEV_DIE_INFO20is_global_id_enabledEj(void *db, unsigned id) {
	if (id == 1174964) // global id of forbidden PCIe block
		return 1;
	bool next_result = is_global_id_enabled_next(db, id);
	if (!next_result) // something else disabled, print it for interest's sake
		fprintf(stderr, "disabled %u\n", id);
	return next_result;
  1. Compile it to a .so file:
gcc -shared -o -fPIC preload_me.c
  1. Launch Quartus with LD_PRELOAD to enable second HIP:
LD_PRELOAD=`pwd`/ /path_to_quartus/intelFPGA/version/quartus/bin/quartus
  1. Instantiate a second PCIe HIP in the design; it'll be placed in the right spot based on the reference clock I/O contstraint

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@alexforencich alexforencich commented Oct 17, 2021

The tools seem to accept 5SGSKF40I3LNAC as a valid part number (either by setting this via the command line or by editing the qsf). However, this does not seem to be a complete solution, as both the GUI and the fitter report that the selected device is 5SGSMD5K2F40I3L (which matches the presentation from Microsoft), but the fitter fails with more than one PCIe core in the design. I wonder if there is some other directive that can be added to the QSF to enable the additional PCIe core, without preloading anything.

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