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Makefile to compile all c files in the directories
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CC :=gcc | |
CPP :=g++ | |
LDFLAGS := | |
C_SOURCES :=$(wildcard *.c) | |
C_EXECUTABLE :=$(C_SOURCES:.c=) | |
CPP_SOURCES :=$(wildcard *.cpp) | |
CPP_EXECUTABLE :=$(CPP_SOURCES:.cpp=) | |
all:$(C_EXECUTABLE) $(CPP_EXECUTABLE) | |
$(C_EXECUTABLE):$(C_SOURCES) | |
$(CC) $< $(LDFLAGS) $(CFLAGS) -o $@ | |
$(CPP_EXECUTABLE):$(CPP_SOURCES) | |
$(CPP) $< $(LDFLAGS) $(CFLAGS) -o $@ | |
clean: | |
rm -rf $(EXECUTABLE) |
Correct me if I am wrong but like this you will build same source file several times and object file will be named differently. I think that problem is in the lines 12 and 15 where automatic variable $<
is used, $<
means first from prerequisites and in this case is some .c file from CPP_SOURCES.
When command from line 12 gets unrolled then you get "gcc some_file.c -o C_EXECUTABLE"
, and in next iteration same file will be used as source file but target will be different.
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@Kareem786-sa
Try
$(shell find . -name '*.c')
or$(shell find . -name '*.cpp')
instead of$(wildcard *.c)