| #include <stdio.h> | |
| #include <stdint.h> | |
| #include <time.h> | |
| #include <limits.h> | |
| #include <assert.h> | |
| #ifndef __aarch64__ | |
| #error This testcase is AArch64 specific and will not work on other processor families. | |
| #endif |
| diff --git a/configure b/configure | |
| index 18c26e0389..ceab414c5b 100755 | |
| --- a/configure | |
| +++ b/configure | |
| @@ -5754,22 +5754,26 @@ if [ "$eventfd" = "yes" ]; then | |
| fi | |
| if test "$softmmu" = yes ; then | |
| - if test "$linux" = yes; then | |
| - if test "$virtfs" != no && test "$cap_ng" = yes && test "$attr" = yes ; then |
| Thoughts on Tachyum (8/7/2020) | |
| Tachyum is a CPU startup that claims that they will | |
| release a VLIW CPU for general purpose use[0], that | |
| would also be faster than a GPU for even AI workloads. | |
| The release of a production processor is planned according | |
| to the company in 2021. However, the company itself says | |
| that they do not have the design working as an FPGA at | |
| this stage, which is a major contradiction. [1] |
This is describing the experience with a retail device, experience on the engineering devices that I played with before was a bit different to say the least...
A Snapdragon 835 laptop for 350 euros, with 4GB of RAM and 64GB of storage. LTE is present but won't be used.
| #!/usr/bin/python | |
| import sys, struct, os | |
| if __name__ == '__main__': | |
| myint = 4 | |
| real_offset = 48 | |
| if len(sys.argv) != 2: | |
| print 'Usage: {} Firmware.bin'.format(sys.argv[0]) | |
| sys.exit(1) | |
| in_file = sys.argv[1] | |
| fp = open(in_file,'rb') |
| RSA32.lib functions: | |
| ARM: | |
| \gmac.obj AesGcmSwitchEndianness | |
| \gmac.obj AesGmacFinal | |
| \gmac.obj AesGmacInit | |
| \gmac.obj AesGmacUpdate | |
| \gmac.obj AesSwapAndXorBlock | |
| \gmac.obj AesXorBlock |
| #include <stdio.h> | |
| #include <windows.h> | |
| #include <bcrypt.h> | |
| #define STATUS_SUCCESS 0x00000000 | |
| int main(void) { | |
| NTSTATUS ntStatus = STATUS_SUCCESS; | |
| BCRYPT_ALG_HANDLE hAlg = NULL; | |
| BCRYPT_KEY_HANDLE hKey = NULL; | |
| ntStatus = BCryptOpenAlgorithmProvider(&hAlg, BCRYPT_RSA_ALGORITHM, MS_PRIMITIVE_PROVIDER, 0); |
| Drawbridge | |
| ========== | |
| Calls from the NTUM to the PAL | |
| ------------------------------ | |
| DkcallSemaphoreRelease | |
| DkcallDebugStringPrint | |
| DkcallSemaphoreCreate | |
| DkcallConsoleNotifyUpdate |
Both iPhone and Watch ship with a Secure Enclave processor. Both are also H11-class SoCs. As such, there are broad similarities between the different blocks. Embedded cores present on-die use firmware written with RTKit, which is Apple's own broadly-used RTOS on cores codenamed Chinook. The codename for the eSIM platform on both the iPhone and Watch is Vinyl. The NFC (+Apple Pay?) controller is named Stockholm, and the Apple Watch Series 4 + iPhone Xs and Xr ship with version 5.
