Some notes for I2C protocool.

I2C Notes.md

I2C Notes

• Rise Time is measured between 30% - 70% of VDD.

Conditions

• START

  HIGH -> LOW when SCL = HIGH

• STOP

  LOW -> HIGH when SCL = HIGH

• START(S) and repeated START are usually functionally identical.
• The bus is considered BUSY after a START condition.
• The bus is considered FREE after a STOP condition.

Hardware Configuration

• The hardware configuration of SDA and SCL are the same. Both of them are pulled up to logic 'high' level by transistors connected to a simple positive supply. Furthermore, all the connected device are OD(Open Drain).
• The bus remains logic 'high' unless the device pulls the bus down.
• To initialize a communication, a device pulls the SDA line low. It should then drive the SCL line with clock pulses until the communication finishes. In this case, the device is the 'master'.

Bus Communication

• 8-bit bytes data followed by a 9th bit for acknowledging generated by the receiving party, until the data transfer is complete.
• The bus is made FREE when the SDA line is released when the SCL line is high (STOP condition is emmited).
• Usually, all the devices should not change SDA line unless the SCL line is low.
• If two masters try to start a communication at the same time, there will be an arbitration to determine the 'winner' and the 'loser'
  • winner: keep control of the bus line and continue the transmission.
  • loser: abort the transmission.

Adressing

• 7-bit addressing: S X X X X X X X R/W A DATA ...
  • A: only one device will acknowledge.
• 10-bit addressing: S 1 1 1 1 0 X X R/W X X X X X X X X X X A2 DATA ...
  • A1: more than one device will acknowledge;
  • A2: only one device will acknowledge.
• R/W: HIGH -> read; LOW -> write.
• A: LOW -> to acknowledge.

Read and Write Operation

bit for bits from slave, bit for bits from master.

• Read Operation: S Slave Address R A DATA A DATA NA P

  • A: each byte of data will be acknowledged by master except (NA) the last byte before the STOP(P).
  • The master is a "MASTER - TRANSMITTER": it transmit both Clock and Data during the whole communication.

• Write Operation: S Slave Address W A DATA A DATA A P

  • The master is a "MASTER TRANSMITTER -> MASTER - RECEIVER": it transmits Clock all the time, but after sending slave address, it becomes a receiver.

• Combined Write and Read: S Slave Address W A DATA A DATA A Sr Slave Address R A DATA A DATA NA P

  • In the Write Operation, each byte of data is acknowledge by the slave;
  • In the Read Operation, except (NA) the last byte of data, each will be acknowledged by the master.

• Combined Read and Write: S Slave Address R A DATA A DATA NA Sr Slave Address W A DATA A DATA A P

  • In the Read Operation, except (NA) the last byte of data before the Sr, each will be acknowledged by the master;
  • In the Write Operation, each byte of data is acknowledge by the slave.

Acknowledge

Acknowledge is done on the 9th clock pulse and is mandatory. SDA line -> LOW.

• Transmitter: release the SDA line;
• Receiver: pulls down the SDA line (SCL must be HIGH);

The transmission will be aborted if no acknowledge.