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February 9, 2019 16:18
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module cordic | |
( | |
input clk, | |
input ce, | |
input rst, | |
input signed [18-1:0] x_in, | |
input signed [18-1:0] y_in, | |
input [18-1:0] phase_in, | |
output signed [18-1:0] sin, | |
output signed [18-1:0] cos | |
); | |
wire [18-1:0] phase_table [0:10-1]; | |
assign phase_table[0] = 32768; | |
assign phase_table[1] = 19344; | |
assign phase_table[2] = 10220; | |
assign phase_table[3] = 5188; | |
assign phase_table[4] = 2604; | |
assign phase_table[5] = 1303; | |
assign phase_table[6] = 651; | |
assign phase_table[7] = 325; | |
assign phase_table[8] = 162; | |
assign phase_table[9] = 81; | |
wire signed [32-1:0] temp_x; | |
wire signed [32-1:0] temp_y; | |
assign temp_x = {{x_in[17]}, x_in, {(32-18-1){1'b0}}}; | |
assign temp_y = {{y_in[17]}, y_in, {(32-18-1){1'b0}}}; | |
reg signed [32-1:0] x [0:11-1]; | |
reg signed [32-1:0] y [0:11-1]; | |
reg signed [18-1:0] phases [0:11-1]; | |
always @(posedge clk) begin | |
if(ce) begin | |
sin <= x[9] >> 14; | |
cos <= y[9] >> 14; | |
case(phase_in[17:15]) | |
0: begin | |
x[0] <= temp_x; | |
y[0] <= temp_y; | |
phases[0] <= phase_in; | |
end | |
1: begin | |
x[0] <= -temp_y; | |
y[0] <= temp_x; | |
phases[0] <= phase_in - 65536; | |
end | |
2: begin | |
x[0] <= -temp_y; | |
y[0] <= temp_x; | |
phases[0] <= phase_in - 65536; | |
end | |
3: begin | |
x[0] <= -temp_x; | |
y[0] <= -temp_y; | |
phases[0] <= phase_in - 131072; | |
end | |
4: begin | |
x[0] <= -temp_x; | |
y[0] <= -temp_y; | |
phases[0] <= phase_in - 131072; | |
end | |
5: begin | |
x[0] <= temp_y; | |
y[0] <= -temp_x; | |
phases[0] <= phase_in - 196608; | |
end | |
6: begin | |
x[0] <= temp_y; | |
y[0] <= -temp_x; | |
phases[0] <= phase_in - 196608; | |
end | |
7: begin | |
x[0] <= temp_x; | |
y[0] <= temp_y; | |
phases[0] <= phase_in; | |
end | |
endcase | |
end | |
end | |
genvar i; | |
generate for(i=0; i<10; i=i+1) begin : gen_for | |
cordic_inner | |
generator_exp | |
( | |
.clk(clk), | |
.ce(ce), | |
.x_in(x[i]), | |
.y_in(y[i]), | |
.p_in(phases[i]), | |
.x_out(x[i + 1]), | |
.y_out(y[i + 1]), | |
.p_out(phases[i + 1]), | |
.p_d(phase_table[i]), | |
.i(i) | |
); | |
end | |
endgenerate | |
endmodule | |
module cordic_inner | |
( | |
input clk, | |
input ce, | |
input signed [32-1:0] x_in, | |
input signed [32-1:0] y_in, | |
input signed [18-1:0] p_in, | |
input signed [18-1:0] p_d, | |
input [32-1:0] i, | |
output signed [32-1:0] x_out, | |
output signed [32-1:0] y_out, | |
output signed [18-1:0] p_out | |
); | |
always @(posedge clk) begin | |
if(ce) begin | |
if(p_in[17]) begin | |
x_out <= x_in + (y_in >> i); | |
y_out <= y_in - (x_in >> i); | |
p_out <= p_in + p_d; | |
end else begin | |
x_out <= x_in - (y_in >> i); | |
y_out <= y_in + (x_in >> i); | |
p_out <= p_in - p_d; | |
end | |
end | |
end | |
endmodule |
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