Generate a package from entities within a VHDL file.

vhdlpckg.pl

# *********************************************************************
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# as published by the Free Software Foundation; either version 2
# of the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
# 02111-1307, USA.
#
# ©2012 - X Engineering Software Systems Corp. (www.xess.com)
# *********************************************************************

# *********************************************************************
# This program reads the entities in a VHDL file and creates
# a package declaration at the top of the file. If a package
# declaration already exists, then any components within it
# are updated and any new components in the VHDL are added.
# *********************************************************************

$comments = '\n((\s*\-\-[^\n]*)\n)*?';
$id       = '\s*([a-z_0-9]*)\s*';

for $fileName (@ARGV) {

    local $/ = undef;

    # Read in VHDL file.
    open( VHDL_IN, $fileName ) || die "$!\n";
    $vhdl = <VHDL_IN>;

    # Extract entity declarations from VHDL and convert into component declarations.
    $vhdlTail = $vhdl;
    $order    = 0;
    while ( $vhdlTail ne '' ) {
        if (
            $vhdlTail =~ /entity $id (is)? .*? \s+ end \s+ entity ($id)? ;/ixs )
        {
            $entityName              = $1;
            $vhdlTail                = $';
            $components{$entityName} = $&;
            $components{$entityName} =~ s/entity/component/ixs;
            $components{$entityName} =~
              s/end \s+ entity ($id)? ;/end component;/ixs;
            $componentOrder[ $order++ ] = $entityName;
        }
        else {
            $vhdlTail = '';
        }
    }

    # Extract packages from VHDL and update components.
    $vhdlHead = '';
    $vhdlTail = $vhdl;
    while ( $vhdlTail ne '' ) {
        if ( $vhdlTail =~
            /package $id (is)? .*? \s+ end \s+ package ($id)? \s* ;/ixs )
        {
            print "In package $1\n";
            $vhdlHead .= $`;
            $vhdlTail    = $';
            $packageName = $1;
            $packageHead = '';
            $packageTail = $&;
            while ( $packageTail ne '' ) {
                if ( $packageTail =~
                    /component $id (is)? .*? \s+ end \s+ component ($id)? ;/ixs
                  )
                {
                    $componentName = $1;
                    $packageHead .= $`;
                    $packageTail = $';
                    if ( exists $components{$componentName} ) {
                        $packageHead .= $components{$componentName};
                        delete $components{$componentName};
                    }
                }
                else {
                    $packageHead .= $packageTail;
                    $packageTail = '';
                }
            }
            $vhdlHead .= $packageHead;
        }
        else {
            $vhdlHead .= $vhdlTail;
            $vhdlTail = '';
        }
    }
    $vhdl = $vhdlHead;

    # Add new components to a package.
    if ( keys %components ) {

        # Add new components to the first package we see.
        if ( $vhdl =~
            /package $id (is)? \s* (.*?\s+) \s* (end \s+ package $id ;)/ixs )
        {
            $vhdlHead    = $` . 'package ' . $1 . "\n\n";
            $packageBody = $3;
            $vhdlTail    = "\n" . $4 . $';
        }

        # No packages in the file, so create one at the top of the file.
        else {
            $vhdlHead    = "\npackage NewPckg is\n\n";
            $packageBody = '';
            $vhdlTail    = "\nend package;\n\n\n\n" . $vhdl;
        }

        # Add components to the package in the order they were defined in the file.
        foreach $componentName (@componentOrder) {
            if ( exists $components{$componentName} ) {
                $packageBody .= $components{$componentName} . "\n";
                delete $components{$componentName};
            }
        }
        $vhdl = $vhdlHead . $packageBody . $vhdlTail;
    }

    open( VHDL_OUT, ">$fileName" ) || die "$!\n";
    print VHDL_OUT $vhdl;
}