tinyfpga fpga uart tx hello world verilog

uart-tx.v

module top(
    input CLK,
    output USBPU,
    output PIN_24,
);
    assign USBPU = 0; // disable USB
    wire clk115200hz;

    dclk0 d0(.clk16mhz(CLK), .clk115200hz(clk115200hz));
    
    //                     P  BBBB BBBB  S  HH
    //                     1  1000 0000  0  00
    //                     1  0987 6543  2  10 
    wire [11:0] seqH = 12'b0__0100_1000__0__11;
    wire [11:0] seqe = 12'b0__0110_0101__0__11;
    wire [11:0] seql = 12'b0__0110_1100__0__11;
    wire [11:0] seqo = 12'b0__0110_1111__0__11;
    wire [11:0] seqA = 12'b0__0000_1010__0__11;
    wire [11:0] seqD = 12'b1__0000_1101__0__11;

    wire [12*7-1:0] seq = {1, seqA, seqD, seqo, seql, seql, seqe, seqH};

    reg [7:0] counter = 0;
    always @(posedge clk115200hz) begin
        counter = counter + 1;
        if (counter == 12*7+1) begin
            counter = 12*7;
        end
    end

    assign PIN_24 = seq[counter];
endmodule

module dclk0(
    input clk16mhz,
    output reg clk115200hz,
);
    reg [8:0] counter;
    always @(posedge clk16mhz) begin
        counter <= counter + 1;
        if (counter == 139/2) begin // 16000000/115200=138.88888...
            counter <= 0;
            clk115200hz <= ~clk115200hz;
        end
    end
endmodule