Add a flush to wishbone-tool uart

file.patch

diff --git a/wishbone-tool/src/bridge/uart.rs b/wishbone-tool/src/bridge/uart.rs
index 0ca9c9a..daf9025 100644
--- a/wishbone-tool/src/bridge/uart.rs
+++ b/wishbone-tool/src/bridge/uart.rs
@@ -239,7 +239,9 @@ impl UartBridge {
         // LiteX ignores the bottom two Wishbone bits, so shift it by
         // two when writing the address.
         serial.write_u32::<BigEndian>(addr >> 2)?;
-        Ok(serial.write_u32::<BigEndian>(value)?)
+        serial.write_u32::<BigEndian>(value)?;
+        serial.flush()?;
+        Ok(())
     }

     fn do_peek<T: SerialPort>(serial: &mut T, addr: u32) -> Result<u32, BridgeError> {