C Project Makefile Template

Makefile

#===============================================================================
# Description: C Project Makefile Template
# Author:
# 
#===============================================================================
#===============================================================================
#  TOOL CHAIN and SHELL TOOL
#===============================================================================
CC = gcc
LD = $(CC)
RM = rm -f

#===============================================================================
#  Project VARS
#===============================================================================
BUILD_DIR = ./build
BIN1      = ${BUILD_DIR}/output
SRCS      = main.c src/foo.c
INCS      = -I./ -I./inc

#===============================================================================
#  CFLAGS, LDFLAGS
#===============================================================================
OPT     = -O2
CFLAGS  = -Wall $(INCS) $(OPT)
LDFLAGS = -s
LDLIBS  = 

#===============================================================================
#  SRCS / OBJS / DEPS
#===============================================================================
OBJS    = ${SRCS:%.c=${BUILD_DIR}/%.o}
DEPS    = ${OBJS:%.o=%.d}

#===============================================================================
#  Targets
#===============================================================================
.PHONY : all clean distclean all-before all-after

all: all-before $(BIN1) all-after

$(BIN1): $(OBJS)
	@echo Linking $@
	@$(LD) -o $@ $^ $(LDFLAGS) $(LDLIBS)
     
clean:
	@$(RM) $(OBJS) $(DEPS) $(BIN1)

distclean:clean
	@$(RM) -r ${BUILD_DIR}

all-before:
	@clear
     
all-after:
	@echo Done @ $$(date)

#===============================================================================
#  Compiling rules
#===============================================================================
-include $(DEPS)

$(BUILD_DIR)/%.o : %.c
	@mkdir -p $(@D)
	@echo Compiling $< ...
	@$(CC) $(CFLAGS) -MMD -c -o $@ $<