lcd blinky example in verilog

lcd_clock.v

`timescale 1ps / 1ps

module lcd_clock (
        input   wire        clk,
        input   wire        rst,
        output  reg         pulse
        );

parameter clk_freq = 26'd12000000;  // X1 = 12MHz
parameter lcd_freq = 26'd4000;      // target output frequency * 2 (2KHz = 4000)

reg [25:0] clk_div;

always @ (posedge clk or posedge rst)
    if (rst) begin
        clk_div <= 0;
        pulse <= 0;
    end else begin
        if (clk_div >= clk_freq/lcd_freq) begin
            clk_div <= 0;
            pulse <= ~pulse;
        end else begin
            clk_div <= clk_div + 1;
        end
    end

endmodule