test_two_bit_comparator.vhd

Library ieee;
Use ieee.std_logic_1164.all;

Entity test_two_bit_comparator is
  -- empty
End test_two_bit_comparator;

Architecture arch of test_two_bit_comparator is

	-- First, get our external comparator
	component two_bit_comparator
		Port (
				InputA, InputB : in std_logic_vector(1 downto 0);
				AEqualsB	: out std_logic
		);
	end component two_bit_comparator;
	
	-- Now, let's create a helper function
	procedure test_values(
		-- define parameters
		Signal in0, in1, in2, in3 : out std_logic;
		Signal compResult	: in std_logic;
		testValue0, testValue1, testValue2, testValue3, expectedResult	: in std_logic
	)
	
		is begin
			in0 <= testValue0;
			in1 <= testValue1;
			in2 <= testValue2;
			in3 <= testValue3;
		wait for 25 ns;
		
		if(not(compResult = expectedResult)) then
			report "TEST FAILED! The simulation is now halted." severity failure;
		end if;
		
		wait for 25 ns;
	end procedure test_values;

	-- Now we can build our wirings
	
	Signal p0, p1, p2, p3, pout	: std_logic;
	begin
              -- [ [1] [0] ] in the table is [ [p0] [p1] ]
		my_test_two_bit_comp : two_bit_comparator port map(InputA(0) => p1, InputB(0) => p3, 
									InputA(1) => p0, InputB(1) => p2, AEqualsB => pout);

	
		test_process : process begin
			test_values(p0,p1,p2,p3,pout,'0','0','0','0','1');
			test_values(p0,p1,p2,p3,pout,'0','0','0','1','0');
			test_values(p0,p1,p2,p3,pout,'0','0','1','0','0');
			test_values(p0,p1,p2,p3,pout,'0','0','1','1','0');

			test_values(p0,p1,p2,p3,pout,'0','1','0','0','0');
			test_values(p0,p1,p2,p3,pout,'0','1','0','1','1');
			test_values(p0,p1,p2,p3,pout,'0','1','1','0','0');
			test_values(p0,p1,p2,p3,pout,'0','1','1','1','0');

			test_values(p0,p1,p2,p3,pout,'1','0','0','0','1');
			test_values(p0,p1,p2,p3,pout,'1','0','0','1','1');
			test_values(p0,p1,p2,p3,pout,'1','0','1','0','0');
			test_values(p0,p1,p2,p3,pout,'1','0','1','1','0');

			test_values(p0,p1,p2,p3,pout,'1','1','0','0','1');
			test_values(p0,p1,p2,p3,pout,'1','1','0','1','1');
			test_values(p0,p1,p2,p3,pout,'1','1','1','0','1');
			test_values(p0,p1,p2,p3,pout,'1','1','1','1','0');
		
			report "None! TEST SUCCESSFUL! End of simulation." severity failure;
		end process test_process;
		
End arch;