Verilog mistmatch between synthesis tools and simulators.

testcase.v

/* Initial design */
module top(input i,
           output reg o);
   reg tmp;
   always @* begin
      o = tmp;
      tmp = i;
   end
endmodule

`ifndef SYNTHESIS
/* Synthesised design (Similar outputs by Quartus and Vivado) */
/* Generated by Yosys 0.9+2406 (git sha1 000fd08198, clang++ 7.1.0 -fPIC -Os) */
module top_synth(i, o);
   input i;
   output o;
   wire tmp;
   assign o = i;
   assign tmp = i;
endmodule

/* Test bench which can be passed to iverilog or verilator */
module main;
   reg i;
   wire o, o_synth;

   top top(i, o);
   top_synth top_synth(i, o_synth);

   initial begin
      i = 0;
      #10 i = 1;
      /* Print the output, where o = 0 and o_synth = 1 */
      #10 $display("o: %d\no_synth: %d", o, o_synth);
      $finish;
   end
endmodule
`endif