Created
June 24, 2015 22:09
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OpenOCD 0.9.0 config for STM32F746G-DISCO target (stm32f746ng)
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# script for stm32f7x family | |
# | |
# stm32 devices support both JTAG and SWD transports. | |
# | |
source [find target/swj-dp.tcl] | |
source [find mem_helper.tcl] | |
if { [info exists CHIPNAME] } { | |
set _CHIPNAME $CHIPNAME | |
} else { | |
set _CHIPNAME stm32f7x | |
} | |
set _ENDIAN little | |
# Work-area is a space in RAM used for flash programming | |
# By default use 128kB | |
if { [info exists WORKAREASIZE] } { | |
set _WORKAREASIZE $WORKAREASIZE | |
} else { | |
set _WORKAREASIZE 0x20000 | |
} | |
#jtag scan chain | |
if { [info exists CPUTAPID] } { | |
set _CPUTAPID $CPUTAPID | |
} else { | |
if { [using_jtag] } { | |
# See STM Document RM0385 | |
# Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0 | |
set _CPUTAPID 0x5ba00477 | |
} { | |
set _CPUTAPID 0x5ba02477 | |
} | |
} | |
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |
if { [info exists BSTAPID] } { | |
set _BSTAPID $BSTAPID | |
} else { | |
# See STM Document RM0385 | |
# Section 40.6.1 | |
# STM32F75xxG | |
set _BSTAPID1 0x06449071 | |
} | |
if {[using_jtag]} { | |
swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ | |
-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ | |
-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 | |
} | |
set _TARGETNAME $_CHIPNAME.cpu | |
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME | |
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |
set _FLASHNAME $_CHIPNAME.flash | |
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME | |
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz | |
# | |
# Since we may be running of an RC oscilator, we crank down the speed a | |
# bit more to be on the safe side. Perhaps superstition, but if are | |
# running off a crystal, we can run closer to the limit. Note | |
# that there can be a pretty wide band where things are more or less stable. | |
adapter_khz 2000 | |
adapter_nsrst_delay 100 | |
if {[using_jtag]} { | |
jtag_ntrst_delay 100 | |
} | |
reset_config srst_nogate | |
if {![using_hla]} { | |
# if srst is not fitted use SYSRESETREQ to | |
# perform a soft reset | |
cortex_m reset_config sysresetreq | |
} | |
$_TARGETNAME configure -event examine-end { | |
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP | |
mmw 0xE0042004 0x00000007 0 | |
# Stop watchdog counters during halt | |
# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP | |
mww 0xE0042008 0x00001800 | |
} | |
$_TARGETNAME configure -event trace-config { | |
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync | |
# change this value accordingly to configure trace pins | |
# assignment | |
mmw 0xE0042004 0x00000020 0 | |
} |
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