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@yodalee
Created January 30, 2023 15:29
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Verilator cmake does not generate right configuration with system-verilog package
cmake_minimum_required(VERSION 3.16)
project(verilog)
find_package(verilator HINTS $ENV{VERILATOR_ROOT})
set(OUT Vmain)
add_executable(${OUT} main.cpp)
verilate(${OUT} TRACE_FST SOURCES out.sv pkg.sv)
#include "Vout.h"
#include <memory>
int main(int argc, char **argv) {
std::unique_ptr<Vout> top{new Vout("top")};
return 0;
}
import pkg::*;
module our (
input clk,
output qbit out
);
always @(posedge clk) begin
begin $display("Hello World"); $finish; end
end
endmodule
package pkg;
typedef logic [4:0] qbit;
endpackage
@codelec
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codelec commented Feb 1, 2023

cmake_minimum_required(VERSION 3.16)

project(verilog)

find_package(verilator HINTS $ENV{VERILATOR_ROOT})

set(OUT Vmain)

add_executable(${OUT} main.cpp)
verilate(${OUT} TRACE_FST PREFIX Vout SOURCES pkg.sv out.sv)

@yodalee
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Author

yodalee commented Feb 1, 2023

Yes this works, thanks.

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