Verilator cmake does not generate right configuration with system-verilog package

CMakeLists.txt

cmake_minimum_required(VERSION 3.16)

project(verilog)

find_package(verilator HINTS $ENV{VERILATOR_ROOT})

set(OUT Vmain)

add_executable(${OUT} main.cpp)
verilate(${OUT} TRACE_FST SOURCES out.sv pkg.sv)

main.cpp

#include "Vout.h"
#include <memory>

int main(int argc, char **argv) {
  std::unique_ptr<Vout> top{new Vout("top")};
  return 0;
}

out.sv

import pkg::*;

module our (
  input clk,
  output qbit out
);

always @(posedge clk) begin
begin $display("Hello World"); $finish; end
end

endmodule

pkg.sv

package pkg;

typedef logic [4:0] qbit;

endpackage

cmake_minimum_required(VERSION 3.16)

project(verilog)

find_package(verilator HINTS $ENV{VERILATOR_ROOT})

set(OUT Vmain)

add_executable(${OUT} main.cpp)
verilate(${OUT} TRACE_FST PREFIX Vout SOURCES pkg.sv out.sv)

Yes this works, thanks.