Created
April 7, 2022 20:41
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uint8_t bcm_spi_transfer(uint8_t value) | |
{ | |
volatile uint32_t* paddr = bcm_spi0 + BCM_SPI0_CS/4; | |
volatile uint32_t* fifo = bcm_spi0 + BCM_SPI0_FIFO/4; | |
uint32_t ret; | |
bcm_peri_set_bits(paddr, BCM_SPI0_CS_CLEAR, BCM_SPI0_CS_CLEAR); | |
/* Set TA = 1, data transfer is active */ | |
bcm_peri_set_bits(paddr, BCM_SPI0_CS_TA, BCM_SPI0_CS_TA); | |
/* Maybe wait for TXD (e.g., if it can't accept any data because the FIFO is full) */ | |
while (!(bcm_peri_read(paddr) & BCM_SPI0_CS_TXD)) | |
; | |
/* Write to FIFO, no barrier */ | |
bcm_peri_write_nb(fifo, bcm_correct_order(value)); | |
/* Wait for DONE to be set */ | |
while (!(bcm_peri_read_nb(paddr) & BCM_SPI0_CS_DONE)) | |
; | |
/* Read any byte that was sent back by the slave while we sere sending to it */ | |
ret = bcm_correct_order(bcm_peri_read_nb(fifo)); | |
/* Set TA = 0 (transfer is finished), and also set the barrier */ | |
bcm_peri_set_bits(paddr, 0, BCM_SPI0_CS_TA); | |
return ret; | |
} |
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