Yu Changyuan yuchangyuan

## sta_cdc_paths.rst

      
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                Timing constraints for clock-domain crossings. #sta #cdc
              
          
    CDC Timing Constraints

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## coding_rtl_for_phys_impl.rst

      
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              July 6, 2023 07:17
            
              
                Tips for physical implementation friendly RTL design. #sta #rtl
              
          
    RTL Coding Tips for Easier Physical Implementation

Quite a few digital design engineers limit their activities to architecture design and RTL coding.
Missing first hand experience with later design phases is then easily detected by how much their
code and architecture complicates physical implementation. Areas where this surfaces most often
are clock/reset schemes, clock domain crossings (CDC) and scan/DFT aspects.

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