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@yuhei1horibe
yuhei1horibe / multiplier.v
Created June 4, 2020 02:22
Adder and multiplier implementation in Verilog
// RCA (Ripple Carry Adder)
module half_adder(
input a,
input b,
output y,
output cout
);
assign cout = a & b; // Carry over
assign y = a ^ b;
endmodule
// SPDX-License-Identifier: GPL-2.0
/*
* Zedboard ASoC sound card support
*
* @author Yuhei Horibe
* Original code: xlnx_pl_snd_card.c
* Reference: zed_adau1761.c
*
* This sound card driver is specific to Zedboard
* Both I2S transmitter and I2S receiver device tree nodes
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
// Add user logic here
wire [4:0]out_from_adder;
// Assign result
always @( posedge S_AXI_ACLK)
begin
if (S_AXI_ARESETN == 1'b0 )
begin
output_reg <= 32'h00000000;
end
my_adder_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) my_adder_v1_0_S00_AXI_inst (
.LED_OUT(led_out),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
input_a_reg <= 0;
input_b_reg <= 0;
//output_reg <= 0;
spare_reg <= 0;
end
else begin
module half_adder(
input a,
input b,
output y,
output cout);
assign cout = a & b; // Carry over