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Helloworld program to debug mm core
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| /****************************************************************************** | |
| * | |
| * Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. | |
| * | |
| * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| * of this software and associated documentation files (the "Software"), to deal | |
| * in the Software without restriction, including without limitation the rights | |
| * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| * copies of the Software, and to permit persons to whom the Software is | |
| * furnished to do so, subject to the following conditions: | |
| * | |
| * The above copyright notice and this permission notice shall be included in | |
| * all copies or substantial portions of the Software. | |
| * | |
| * Use of the Software is limited solely to applications: | |
| * (a) running on a Xilinx device, or | |
| * (b) that interact with a Xilinx device through a bus or interconnect. | |
| * | |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF | |
| * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
| * SOFTWARE. | |
| * | |
| * Except as contained in this notice, the name of the Xilinx shall not be used | |
| * in advertising or otherwise to promote the sale, use or other dealings in | |
| * this Software without prior written authorization from Xilinx. | |
| * | |
| ******************************************************************************/ | |
| /* | |
| * helloworld.c: simple test application | |
| * | |
| * This application configures UART 16550 to baud rate 9600. | |
| * PS7 UART (Zynq) is not initialized by this application, since | |
| * bootrom/bsp configures it to baud rate 115200 | |
| * | |
| * ------------------------------------------------ | |
| * | UART TYPE BAUD RATE | | |
| * ------------------------------------------------ | |
| * uartns550 9600 | |
| * uartlite Configurable only in HW design | |
| * ps7_uart 115200 (configured by bootrom/bsp) | |
| */ | |
| #include <stdio.h> | |
| #include "platform.h" | |
| #include "xil_printf.h" | |
| #include "xil_io.h" | |
| #include "xaxidma.h" | |
| #include "xparameters.h" | |
| #ifndef __aarch64__ | |
| #define __aarch64__ | |
| #endif | |
| #define DMA_DEV_ID XPAR_AXIDMA_0_DEVICE_ID | |
| #ifdef XPAR_AXI_7SDDR_0_S_AXI_BASEADDR | |
| #define DDR_BASE_ADDR XPAR_AXI_7SDDR_0_S_AXI_BASEADDR | |
| #elif defined (XPAR_MIG7SERIES_0_BASEADDR) | |
| #define DDR_BASE_ADDR XPAR_MIG7SERIES_0_BASEADDR | |
| #elif defined (XPAR_MIG_0_BASEADDR) | |
| #define DDR_BASE_ADDR XPAR_MIG_0_BASEADDR | |
| #elif defined (XPAR_PSU_DDR_0_S_AXI_BASEADDR) | |
| #define DDR_BASE_ADDR XPAR_PSU_DDR_0_S_AXI_BASEADDR | |
| #endif | |
| #ifndef DDR_BASE_ADDR | |
| #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \ | |
| DEFAULT SET TO 0x01000000 | |
| #define MEM_BASE_ADDR 0x01000000 | |
| #else | |
| #define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000) | |
| #endif | |
| #define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000) | |
| #define RX_BUFFER_BASE (MEM_BASE_ADDR + 0x00300000) | |
| #define RX_BUFFER_HIGH (MEM_BASE_ADDR + 0x004FFFFF) | |
| #define MAX_TX_PKT_LEN 2*48*4 | |
| #define MAX_RX_PKT_LEN 2*64*4 | |
| int XAxiDma_SimplePollExample(u16 DeviceId); | |
| static int CheckData(void); | |
| XAxiDma AxiDma; | |
| int main() | |
| { | |
| init_platform(); | |
| print("Hello World\n\r"); | |
| //u32 mxv_0 = 0x80001000; | |
| u32 abc_aux_cmd = 0xA0002000; | |
| u32 abc_load_cmd = 0xA0004000; | |
| u32 abc_macc_cmd = 0xA0008000; | |
| //u32 axi_dma = 0x80000000; | |
| //slave register 0, test_en, rst_n | |
| //Xil_Out32(mxv_0, 0b00); | |
| //Xil_Out32(mxv_0, 0b01); | |
| //Xil_Out32(mxv_0 + 0x4, (15<<16)+7); | |
| //Xil_Out32(mxv_0 + 0x8, (7<<16)+7); | |
| //aux_cmd - 32b | |
| Xil_Out32(abc_aux_cmd, 0b1000000000100); | |
| Xil_Out32(abc_aux_cmd + 0x4, 0b1000000001100); | |
| Xil_Out32(abc_aux_cmd + 0x8, 0b1000000010100); | |
| Xil_Out32(abc_aux_cmd + 0xc, 0b1000000011100); | |
| Xil_Out32(abc_aux_cmd + 0x10, 0b1000000100100); | |
| Xil_Out32(abc_aux_cmd + 0x14, 0b1000000101100); | |
| Xil_Out32(abc_aux_cmd + 0x18, 0b1000000110100); | |
| Xil_Out32(abc_aux_cmd + 0x1c, 0b1000000111110); | |
| //load_cmd - 128b | |
| Xil_Out32(abc_load_cmd, 0b00000000000000001000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x4, 0b00000000000000001000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x8, 0b1000001110010000000000000000001); | |
| Xil_Out32(abc_load_cmd + 0xc, 0b0); | |
| Xil_Out32(abc_load_cmd + 0x10, 0b00000000000000001000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x14, 0b00000000000000001000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x18, 0b1010001110010000000000000000001); | |
| Xil_Out32(abc_load_cmd + 0x1c, 0b0); | |
| Xil_Out32(abc_load_cmd + 0x20, 0b00000000000000001000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x24, 0b00000000000000001000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x28, 0b1100001110010000000000000000001); | |
| Xil_Out32(abc_load_cmd + 0x2c, 0b0); | |
| Xil_Out32(abc_load_cmd + 0x30, 0b00000000000000001000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x34, 0b00000000000000001000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x38, 0b1110001111010000000000000000001); | |
| Xil_Out32(abc_load_cmd + 0x3c, 0b0); | |
| Xil_Out32(abc_load_cmd + 0x40, 0b00000000000000000000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x44, 0b00000000000000000000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x48, 0b1000001110100000000000000000001); | |
| Xil_Out32(abc_load_cmd + 0x4c, 0b0); | |
| Xil_Out32(abc_load_cmd + 0x50, 0b00000000000000000000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x54, 0b00000000000000000000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x58, 0b1010001110100000000000000000001); | |
| Xil_Out32(abc_load_cmd + 0x5c, 0b0); | |
| Xil_Out32(abc_load_cmd + 0x60, 0b00000000000000000000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x64, 0b00000000000000000000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x68, 0b1100001110100000000000000000001); | |
| Xil_Out32(abc_load_cmd + 0x6c, 0b0); | |
| Xil_Out32(abc_load_cmd + 0x70, 0b00000000000000000000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x74, 0b00000000000000000000000000000000); | |
| Xil_Out32(abc_load_cmd + 0x78, 0b1110001111100000000000000000001); | |
| Xil_Out32(abc_load_cmd + 0x7c, 0b0); | |
| /* load_data - 32b x 2 | |
| Xil_Out32(abc_load_data, 0b01100100110101000111011111010011); | |
| Xil_Out32(abc_load_data + 0x4, 0b01101100000111100011111100110110); | |
| Xil_Out32(abc_load_data + 0x8, 0b11001011100110011011111100110111); | |
| Xil_Out32(abc_load_data + 0xc, 0b11101111001010101101001011101110); | |
| Xil_Out32(abc_load_data + 0x10, 0b01110101001101111000011010100011); | |
| Xil_Out32(abc_load_data + 0x14, 0b00101000100111011001001001011000); | |
| Xil_Out32(abc_load_data + 0x18, 0b01010000110010000000001011001010); | |
| Xil_Out32(abc_load_data + 0x1c, 0b10011110011001011000010100011110); | |
| abc_load_data += 512; | |
| Xil_Out32(abc_load_data, 0b00111110011011000010001110110011); | |
| Xil_Out32(abc_load_data + 0x4, 0b01100011010001111100101011110101); | |
| Xil_Out32(abc_load_data + 0x8, 0b01001001111000011001001111101010); | |
| Xil_Out32(abc_load_data + 0xc, 0b00000100100010011010100111101100); | |
| Xil_Out32(abc_load_data + 0x10, 0b00101011001000000100110111110001); | |
| Xil_Out32(abc_load_data + 0x14, 0b11001001011110111001010100001000); | |
| Xil_Out32(abc_load_data + 0x18, 0b11001100110011010101111000001110); | |
| Xil_Out32(abc_load_data + 0x1c, 0b00100111110100010010110111110010); | |
| */ | |
| //macc_cmd - 256b | |
| Xil_Out32(abc_macc_cmd, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x4, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xc, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x10, 0xe1002000); | |
| Xil_Out32(abc_macc_cmd + 0x14, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x18, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1c, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x20, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x24, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x28, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x2c, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x30, 0xe100a000); | |
| Xil_Out32(abc_macc_cmd + 0x34, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x38, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x3c, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x40, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x44, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x48, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x4c, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x50, 0xe1012000); | |
| Xil_Out32(abc_macc_cmd + 0x54, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x58, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x5c, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x60, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x64, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x68, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x6c, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x70, 0xe101a000); | |
| Xil_Out32(abc_macc_cmd + 0x74, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x78, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x7c, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x80, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x84, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x88, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x8c, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x90, 0xe1022000); | |
| Xil_Out32(abc_macc_cmd + 0x94, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x98, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x9c, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xa0, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xa4, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xa8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xac, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0xb0, 0xe102a000); | |
| Xil_Out32(abc_macc_cmd + 0xb4, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0xb8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xbc, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xc0, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xc4, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xc8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xcc, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0xd0, 0xe1032000); | |
| Xil_Out32(abc_macc_cmd + 0xd4, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0xd8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xdc, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xe0, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xe4, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xe8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xec, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0xf0, 0xf103a000); | |
| Xil_Out32(abc_macc_cmd + 0xf4, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0xf8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0xfc, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x100, 0x00001004); | |
| Xil_Out32(abc_macc_cmd + 0x104, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x108, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x10c, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x110, 0xec002000); | |
| Xil_Out32(abc_macc_cmd + 0x114, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x118, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x11c, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x120, 0x0000100c); | |
| Xil_Out32(abc_macc_cmd + 0x124, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x128, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x12c, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x130, 0xec00a000); | |
| Xil_Out32(abc_macc_cmd + 0x134, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x138, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x13c, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x140, 0x00001014); | |
| Xil_Out32(abc_macc_cmd + 0x144, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x148, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x14c, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x150, 0xec012000); | |
| Xil_Out32(abc_macc_cmd + 0x154, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x158, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x15c, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x160, 0x0000101c); | |
| Xil_Out32(abc_macc_cmd + 0x164, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x168, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x16c, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x170, 0xec01a000); | |
| Xil_Out32(abc_macc_cmd + 0x174, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x178, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x17c, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x180, 0x00001024); | |
| Xil_Out32(abc_macc_cmd + 0x184, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x188, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x18c, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x190, 0xec022000); | |
| Xil_Out32(abc_macc_cmd + 0x194, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x198, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x19c, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1a0, 0x0000102c); | |
| Xil_Out32(abc_macc_cmd + 0x1a4, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1a8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1ac, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x1b0, 0xec02a000); | |
| Xil_Out32(abc_macc_cmd + 0x1b4, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x1b8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1bc, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1c0, 0x00001034); | |
| Xil_Out32(abc_macc_cmd + 0x1c4, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1c8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1cc, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x1d0, 0xec032000); | |
| Xil_Out32(abc_macc_cmd + 0x1d4, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x1d8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1dc, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1e0, 0x0000103e); | |
| Xil_Out32(abc_macc_cmd + 0x1e4, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1e8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1ec, 0x00000800); | |
| Xil_Out32(abc_macc_cmd + 0x1f0, 0xfc03a000); | |
| Xil_Out32(abc_macc_cmd + 0x1f4, 0x00000098); | |
| Xil_Out32(abc_macc_cmd + 0x1f8, 0x0); | |
| Xil_Out32(abc_macc_cmd + 0x1fc, 0x0); | |
| /*macc_data - 32b x 2 | |
| Xil_Out32(abc_macc_data, 0b00000000111101110000000010111111); | |
| Xil_Out32(abc_macc_data + 0x4, 0b00000000111100000000000001110001); | |
| Xil_Out32(abc_macc_data + 0x8, 0b00000000001001000000000010000010); | |
| Xil_Out32(abc_macc_data + 0xc, 0b00000000000100010000000001011000); | |
| Xil_Out32(abc_macc_data + 0x10, 0b00000000001010110000000000110000); | |
| Xil_Out32(abc_macc_data + 0x14, 0b00000000110110100000000011000100); | |
| Xil_Out32(abc_macc_data + 0x18, 0b00000000010101100000000011101011); | |
| Xil_Out32(abc_macc_data + 0x1c, 0b00000000100110110000000010111010); | |
| Xil_Out32(abc_macc_data + 0x20, 0b00000000011010010000000001111101); | |
| Xil_Out32(abc_macc_data + 0x24, 0b00000000011000100000000010001011); | |
| Xil_Out32(abc_macc_data + 0x28, 0b00000000010111000000000001111101); | |
| Xil_Out32(abc_macc_data + 0x2c, 0b00000000111100100000000010110001); | |
| Xil_Out32(abc_macc_data + 0x30, 0b00000000011111100000000011001111); | |
| Xil_Out32(abc_macc_data + 0x34, 0b00000000011000000000000000100101); | |
| Xil_Out32(abc_macc_data + 0x38, 0b00000000011101000000000011101001); | |
| Xil_Out32(abc_macc_data + 0x3c, 0b00000000000110100000000000010111); | |
| abc_macc_data += 512; | |
| Xil_Out32(abc_macc_data, 0b00000000100011010000000010110111); | |
| Xil_Out32(abc_macc_data + 0x4, 0b00000000000001010000000011110111); | |
| Xil_Out32(abc_macc_data + 0x8, 0b00000000101100110000000001000100); | |
| Xil_Out32(abc_macc_data + 0xc, 0b00000000110101010000000001011100); | |
| Xil_Out32(abc_macc_data + 0x10, 0b00000000100000100000000001010010); | |
| Xil_Out32(abc_macc_data + 0x14, 0b00000000111010010000000001000010); | |
| Xil_Out32(abc_macc_data + 0x18, 0b00000000111010000000000000011110); | |
| Xil_Out32(abc_macc_data + 0x1c, 0b00000000001100000000000010100111); | |
| Xil_Out32(abc_macc_data + 0x20, 0b00000000110110000000000010011011); | |
| Xil_Out32(abc_macc_data + 0x24, 0b00000000101100010000000010000110); | |
| Xil_Out32(abc_macc_data + 0x28, 0b00000000110111010000000010101110); | |
| Xil_Out32(abc_macc_data + 0x2c, 0b00000000100110010000000000111110); | |
| Xil_Out32(abc_macc_data + 0x30, 0b00000000101111000000000011000101); | |
| Xil_Out32(abc_macc_data + 0x34, 0b00000000111000010000000010101100); | |
| Xil_Out32(abc_macc_data + 0x38, 0b00000000101011110000000010111011); | |
| Xil_Out32(abc_macc_data + 0x3c, 0b00000000110010000000000011010100); | |
| */ | |
| // axi dma transaction | |
| int ret; | |
| ret = XAxiDma_SimplePollExample(XPAR_AXI_DMA_0_DEVICE_ID); | |
| printf("Completed with status %d\n\r", ret); | |
| cleanup_platform(); | |
| return 0; | |
| } | |
| /*****************************************************************************/ | |
| /** | |
| * The example to do the simple transfer through polling. The constant | |
| * NUMBER_OF_TRANSFERS defines how many times a simple transfer is repeated. | |
| * | |
| * @param DeviceId is the Device Id of the XAxiDma instance | |
| * | |
| * @return | |
| * - XST_SUCCESS if example finishes successfully | |
| * - XST_FAILURE if error occurs | |
| * | |
| * @note None | |
| * | |
| * | |
| ******************************************************************************/ | |
| int XAxiDma_SimplePollExample(u16 DeviceId) | |
| { | |
| XAxiDma_Config *CfgPtr; | |
| int Status; | |
| int Tries = 1; | |
| int Index; | |
| int offset; | |
| u8 *TxBufferPtr; | |
| u8 *RxBufferPtr; | |
| u32 *TxWordPtr; | |
| TxBufferPtr = (u8 *)TX_BUFFER_BASE; | |
| RxBufferPtr = (u8 *)RX_BUFFER_BASE; | |
| /* Initialize the XAxiDma device. | |
| */ | |
| CfgPtr = XAxiDma_LookupConfig(DeviceId); | |
| if (!CfgPtr) { | |
| xil_printf("No config found for %d\r\n", DeviceId); | |
| return XST_FAILURE; | |
| } | |
| Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr); | |
| if (Status != XST_SUCCESS) { | |
| xil_printf("Initialization failed %d\r\n", Status); | |
| return XST_FAILURE; | |
| } | |
| if(XAxiDma_HasSg(&AxiDma)){ | |
| xil_printf("Device configured as SG mode \r\n"); | |
| return XST_FAILURE; | |
| } | |
| /* Disable interrupts, we use polling mode | |
| */ | |
| XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, | |
| XAXIDMA_DEVICE_TO_DMA); | |
| XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, | |
| XAXIDMA_DMA_TO_DEVICE); | |
| /* | |
| Value = TEST_START_VALUE; | |
| for(Index = 0; Index < MAX_PKT_LEN; Index ++) { | |
| TxBufferPtr[Index] = Value; | |
| Value = (Value + 1) & 0xFF; | |
| } | |
| */ | |
| TxWordPtr = (u32 *)TX_BUFFER_BASE; | |
| for(Index = 0; Index < 2; Index ++) { | |
| offset = 48*Index; | |
| // load data | |
| TxWordPtr[offset+0] = 0b01100100110101000111011111010011; | |
| TxWordPtr[offset+1] = 0b01101100000111100011111100110110; | |
| TxWordPtr[offset+2] = 0b11001011100110011011111100110111; | |
| TxWordPtr[offset+3] = 0b11101111001010101101001011101110; | |
| TxWordPtr[offset+4] = 0b01110101001101111000011010100011; | |
| TxWordPtr[offset+5] = 0b00101000100111011001001001011000; | |
| TxWordPtr[offset+6] = 0b01010000110010000000001011001010; | |
| TxWordPtr[offset+7] = 0b10011110011001011000010100011110; | |
| TxWordPtr[offset+8] = 0b00111110011011000010001110110011; | |
| TxWordPtr[offset+9] = 0b01100011010001111100101011110101; | |
| TxWordPtr[offset+10] = 0b01001001111000011001001111101010; | |
| TxWordPtr[offset+11] = 0b00000100100010011010100111101100; | |
| TxWordPtr[offset+12] = 0b00101011001000000100110111110001; | |
| TxWordPtr[offset+13] = 0b11001001011110111001010100001000; | |
| TxWordPtr[offset+14] = 0b11001100110011010101111000001110; | |
| TxWordPtr[offset+15] = 0b00100111110100010010110111110010; | |
| // macc data | |
| TxWordPtr[offset+16] = 0b00000000111101110000000010111111; | |
| TxWordPtr[offset+17] = 0b00000000111100000000000001110001; | |
| TxWordPtr[offset+18] = 0b00000000001001000000000010000010; | |
| TxWordPtr[offset+19] = 0b00000000000100010000000001011000; | |
| TxWordPtr[offset+20] = 0b00000000001010110000000000110000; | |
| TxWordPtr[offset+21] = 0b00000000110110100000000011000100; | |
| TxWordPtr[offset+22] = 0b00000000010101100000000011101011; | |
| TxWordPtr[offset+23] = 0b00000000100110110000000010111010; | |
| TxWordPtr[offset+24] = 0b00000000011010010000000001111101; | |
| TxWordPtr[offset+25] = 0b00000000011000100000000010001011; | |
| TxWordPtr[offset+26] = 0b00000000010111000000000001111101; | |
| TxWordPtr[offset+27] = 0b00000000111100100000000010110001; | |
| TxWordPtr[offset+28] = 0b00000000011111100000000011001111; | |
| TxWordPtr[offset+29] = 0b00000000011000000000000000100101; | |
| TxWordPtr[offset+30] = 0b00000000011101000000000011101001; | |
| TxWordPtr[offset+31] = 0b00000000000110100000000000010111; | |
| TxWordPtr[offset+32] = 0b00000000100011010000000010110111; | |
| TxWordPtr[offset+33] = 0b00000000000001010000000011110111; | |
| TxWordPtr[offset+34] = 0b00000000101100110000000001000100; | |
| TxWordPtr[offset+35] = 0b00000000110101010000000001011100; | |
| TxWordPtr[offset+36] = 0b00000000100000100000000001010010; | |
| TxWordPtr[offset+37] = 0b00000000111010010000000001000010; | |
| TxWordPtr[offset+38] = 0b00000000111010000000000000011110; | |
| TxWordPtr[offset+39] = 0b00000000001100000000000010100111; | |
| TxWordPtr[offset+40] = 0b00000000110110000000000010011011; | |
| TxWordPtr[offset+41] = 0b00000000101100010000000010000110; | |
| TxWordPtr[offset+42] = 0b00000000110111010000000010101110; | |
| TxWordPtr[offset+43] = 0b00000000100110010000000000111110; | |
| TxWordPtr[offset+44] = 0b00000000101111000000000011000101; | |
| TxWordPtr[offset+45] = 0b00000000111000010000000010101100; | |
| TxWordPtr[offset+46] = 0b00000000101011110000000010111011; | |
| TxWordPtr[offset+47] = 0b00000000110010000000000011010100; | |
| } | |
| /* Flush the SrcBuffer before the DMA transfer, in case the Data Cache | |
| * is enabled | |
| */ | |
| Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_TX_PKT_LEN); | |
| #ifdef __aarch64__ | |
| Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_RX_PKT_LEN); | |
| #endif | |
| for(Index = 0; Index < Tries; Index ++) { | |
| Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxBufferPtr, | |
| MAX_RX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA); | |
| if (Status != XST_SUCCESS) { | |
| return XST_FAILURE; | |
| } | |
| Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) TxBufferPtr, | |
| MAX_TX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE); | |
| if (Status != XST_SUCCESS) { | |
| return XST_FAILURE; | |
| } | |
| while (XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA)) { | |
| /* Wait */ | |
| } | |
| while (XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE)) { | |
| /* Wait */ | |
| } | |
| Status = CheckData(); | |
| if (Status != XST_SUCCESS) { | |
| return XST_FAILURE; | |
| } | |
| } | |
| /* Test finishes successfully | |
| */ | |
| return XST_SUCCESS; | |
| } | |
| /*****************************************************************************/ | |
| /* | |
| * | |
| * This function checks data buffer after the DMA transfer is finished. | |
| * | |
| * @param None | |
| * | |
| * @return | |
| * - XST_SUCCESS if validation is successful. | |
| * - XST_FAILURE otherwise. | |
| * | |
| * @note None. | |
| * | |
| ******************************************************************************/ | |
| static int CheckData(void) | |
| { | |
| u8 *RxPacket; | |
| int Index = 0; | |
| RxPacket = (u8 *) RX_BUFFER_BASE; | |
| /* Invalidate the DestBuffer before receiving the data, in case the | |
| * Data Cache is enabled | |
| */ | |
| #ifndef __aarch64__ | |
| Xil_DCacheInvalidateRange((UINTPTR)RxPacket, MAX_RX_PKT_LEN); | |
| #endif | |
| for(Index = 0; Index < 64; Index++) { | |
| printf("Output data %d: %x \r\n", | |
| Index, (unsigned int)RxPacket[Index]); | |
| } | |
| return XST_SUCCESS; | |
| } |
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