Verilog Examples

four.vh

module four(clk, set, out);
// An example for counter

	input clk, set;
	output [3:0] out;
	reg [3:0] out;

	always @ (posedge clk)
	begin
		if (set)
			out = 4'b1111;
			// assign 1111 to out
		else
			out = out + 1'b1;
			// add 1 to out
	end

endmodule

one.vh

module one(out, in_a, in_b);

	input in_a, in_b;
	output out;

	and and_a(out, in_a, in_b);

endmodule

three.vh

module three(d, clk, reset, q, q_invert);
// An example for D flip-flop

	input d, clk, reset;
	output q, q_invert;
	reg q;
	assign q_invert = ~q;

	always @ (posedge clk or posedge reset)
	// Syntax: sth | posedge sth | negedge sth
	begin
		if (reset)
			begin
				q <= 1'b0;
				// assign 0 to q
				// Use <= for simultaneous assignment
				// Use = for step-by-step assignment
			end
		else
			begin
				q <= d;
				// assign d to q
			end
	end

endmodule

two.vh

module mux2to1(out, i1, i2, s1);

	input i1, i2, s1;
	output out;
	wire s1_invert, temp1, temp2;

	not not_a(s1_invert, s1);
	and and_a(temp1, i1, s1_invert);
	and and_b(temp2, i2, s1);
	or or_a(out, temp1, temp2);

endmodule

module two(out1, out2, i1, i2, s1, i3, i4, s2);

	input i1, i2, s1, i3, i4, s2;
	output out1, out2;

	mux2to1(out1, i1, i2, s1);
	mux2to1(out2, i3, i4, s2);

endmodule