SquareWaveGenerator.vhd

----------------------------------------------------------------------------------
-- Company: Koc University
-- Engineer: Zafer Cavdar & Cisem Altan
-- 
-- Create Date:    23:11:44 04/30/2016 
-- Design Name:    PSWG
-- Module Name:    ProjectCode - Behavioral 
-- Project Name:   Programmable Square Wave Generator
-- Target Devices: Basys 2 Spartan 3E CP 132 FPGA Board
-- Tool versions: 
-- Description: Elec 204 - Lab Final Project Spring 2016
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ProjectCode is
    Port ( CLK : in STD_LOGIC;
			  N : in  STD_LOGIC_VECTOR (3 downto 0);
           M : in  STD_LOGIC_VECTOR (3 downto 0);
			  SEVEN_SEG_DISPLAY : OUT STD_LOGIC_VECTOR(6 downto 0);
			  ANODES : out STD_LOGIC_VECTOR(3 downto 0) := "1111";
			  N_OUTPUT : out STD_LOGIC_VECTOR(3 downto 0);
			  M_OUTPUT : out STD_LOGIC_VECTOR(3 downto 0);
			  OSCILLOSCOPE : out STD_LOGIC; -- pmod output portuna baglanacak
			  LED : out STD_LOGIC);
end ProjectCode;

architecture Behavioral of ProjectCode is
	signal COUNT_M : STD_LOGIC_VECTOR(3 downto 0):="0001";
	signal COUNT_N : STD_LOGIC_VECTOR(3 downto 0):="0001";
	signal SELECTOR : STD_LOGIC:='0';
	signal SEVEN_SEG_INPUT : STD_LOGIC_VECTOR(3 downto 0):="0000";
	signal NA : STD_LOGIC_VECTOR(3 downto 0);
	signal NB : STD_LOGIC_VECTOR(3 downto 0);
	signal MA : STD_LOGIC_VECTOR(3 downto 0);
	signal MB : STD_LOGIC_VECTOR(3 downto 0);
	
begin
	process(CLK)
	variable counter : integer := 0;
	variable segCount1 : integer :=0;
	variable segCount2 : integer :=0;
	variable segCount3 : integer :=0;
	variable segCount4 : integer :=0;
	variable inc1 : integer := 1;
	variable inc2 : integer := 0;
	variable inc3 : integer := 0;
	variable inc4 : integer := 0;
	
	begin
		if (rising_edge(CLK)) then
			counter := counter + 1;
			segCount1 := segCount1 + inc1;
			segCount2 := segCount2 + inc2;
			segCount3 := segCount3 + inc3;
			segCount4 := segCount4 + inc4;
			
			if (segCount1 = 50000) then
				segCount1 := 0;
				inc1 := 0;
				inc2 := 1;
				inc3 := 0;
				inc4 := 0;
				ANODES <= "1110";
				SEVEN_SEG_INPUT <= NA;
			end if;
			
			if (segCount2 = 50000) then
				segCount2 := 0;
				inc1 := 0;
				inc2 := 0;
				inc3 := 1;
				inc4 := 0;
				ANODES <= "1101";
				SEVEN_SEG_INPUT <= NB;
			end if;
			
			if (segCount3 = 50000) then
				segCount3 := 0;
				inc1 := 0;
				inc2 := 0;
				inc3 := 0;
				inc4 := 1;
				ANODES <= "1011";
				SEVEN_SEG_INPUT <= MA;
			end if;
			
			if (segCount4 = 50000) then
				segCount4 := 0;
				inc1 := 1;
				inc2 := 0;
				inc3 := 0;
				inc4 := 0;
				ANODES <= "0111";
				SEVEN_SEG_INPUT <= MB;
			end if;
			
			
			if (counter = 5) then
		
				IF (COUNT_M > M or COUNT_M = M) AND (SELECTOR = '1') THEN
					COUNT_M <= "0001";
					if (not (N = "0000")) then
						SELECTOR <= '0';
					end if;
				elsif (SELECTOR = '1') then
					COUNT_M <= COUNT_M+1;
				END IF;
				
				IF (COUNT_N > N or COUNT_N = N) AND (SELECTOR = '0') THEN
					COUNT_N <= "0001";
					if (not (M = "0000")) then
						SELECTOR <= '1';
					end if;
				elsif (SELECTOR = '0') then
					COUNT_N <= COUNT_N+1;
				END IF;
				
				
				counter := 0;
			end if;
		end if;
	end process;
	
	LED <= SELECTOR;
	OSCILLOSCOPE <= SELECTOR;
	N_OUTPUT <= COUNT_N;
	M_OUTPUT <= COUNT_M;	

	NA(3) <= '0';
	NA(2) <= '0';
	NA(1) <= '0';
	NA(0) <= (N(3) and N(2)) or (N(3) and N(1));
	NB(3) <= N(3) and not N(2) and not N(1);
	NB(2) <= (not N(3) and N(2)) or (N(2) and N(1));
	NB(1) <= (N(3)and N(2) and not N(1)) or (not N(3) and N(1));
	NB(0) <= N(0);
	
	MA(3) <= '0';
	MA(2) <= '0';
	MA(1) <= '0';
	MA(0) <= (M(3) and M(2)) or (M(3) and M(1));
	MB(3) <= M(3) and not M(2) and not M(1);
	MB(2) <= (not M(3) and M(2)) or (M(2) and M(1));
	MB(1) <= (M(3)and M(2) and not M(1)) or (not M(3) and M(1));
	MB(0) <= M(0);

	
	with SEVEN_SEG_INPUT select
		SEVEN_SEG_DISPLAY <= "0000001" when "0000",
										"1001111" when "0001",
										"0010010" when "0010",
										"0000110" when "0011",
										"1001100" when "0100",
										"0100100" when "0101",
										"0100000" when "0110",
										"0001111" when "0111",
										"0000000" when "1000",
										"0000100" when "1001",
										"0001000" when "1010",
										"1100000" when "1011",
										"0110001" when "1100",
										"1000010" when "1101",
										"0110000" when "1110",
										"0111000" when "1111",
										"1111111" when others;
	
end Behavioral;