excerpts from /sys/kernel/debug/clk/clk_summary

==> 2k_and_dsi <==

                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
    pll-video0                        2        2        2   297000000          0     0  50000
       dsi-dphy                       1        1        1   148500000          0     0  50000
       pll-mipi                       1        1        1   297000000          0     0  50000
          tcon0                       1        1        1   297000000          0     0  50000
             tcon-pixel-clock         1        1        1    27000000          0     0  50000
       pll-video0-2x                  0        0        0   594000000          0     0  50000
    pll-video1                        3        3        1   204000000          0     0  50000
       hdmi-phy-clk                   1        1        0   204000000          0     0  50000
       hdmi                           1        1        0   204000000          0     0  50000
       tcon1                          1        1        1   204000000          0     0  50000

==> 2k_only <==

                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
    pll-video0                        3        3        1   204000000          0     0  50000
       hdmi-phy-clk                   1        1        0   204000000          0     0  50000
       dsi-dphy                       0        0        0   204000000          0     0  50000
       hdmi                           1        1        0   204000000          0     0  50000
       tcon1                          1        1        1   204000000          0     0  50000
       pll-mipi                       0        0        0   408000000          0     0  50000
          tcon0                       0        0        0   408000000          0     0  50000
       pll-video0-2x                  0        0        0   408000000          0     0  50000
    pll-video1                        0        0        0   297000000          0     0  50000

==> dsi_only <==

                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
    pll-video1                        0        0        0   297000000          0     0  50000
    pll-video0                        4        4        2   297000000          0     0  50000
       hdmi-phy-clk                   1        1        0    74250000          0     0  50000
       dsi-dphy                       1        1        1   148500000          0     0  50000
       hdmi                           1        1        0   297000000          0     0  50000
       tcon1                          0        0        0   297000000          0     0  50000
       pll-mipi                       1        1        1   297000000          0     0  50000
          tcon0                       1        1        1   297000000          0     0  50000
             tcon-pixel-clock         1        1        1    27000000          0     0  50000
       pll-video0-2x                  0        0        0   594000000          0     0  50000

==> fullhd_and_dsi <==

                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
    pll-video0                        3        3        1   293333333          0     0  50000
       hdmi-phy-clk                   1        1        0   146666666          0     0  50000
       dsi-dphy                       0        0        0   293333333          0     0  50000
       hdmi                           1        1        0   146666667          0     0  50000
       tcon1                          1        1        1   146666667          0     0  50000
       pll-mipi                       0        0        0   586666666          0     0  50000
          tcon0                       0        0        0   586666666          0     0  50000
       pll-video0-2x                  0        0        0   586666666          0     0  50000
    pll-video1                        0        0        0   297000000          0     0  50000

==> fullhd_only <==

                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
    pll-video0                        2        2        2   297000000          0     0  50000
       dsi-dphy                       1        1        1   148500000          0     0  50000
       pll-mipi                       1        1        1   297000000          0     0  50000
          tcon0                       1        1        1   297000000          0     0  50000
             tcon-pixel-clock         1        1        1    27000000          0     0  50000
       pll-video0-2x                  0        0        0   594000000          0     0  50000
    pll-video1                        3        3        1   293333333          0     0  50000
       hdmi-phy-clk                   1        1        0   146666666          0     0  50000
       hdmi                           1        1        0   146666667          0     0  50000
       tcon1                          1        1        1   146666667          0     0  50000