Anduril ADC fix

cfg-lexel_2S.h

// Lexel 2S config options for Anduril
#include "hwdef-Lexel_2S.h"

// ../../bin/level_calc.py 1 65 7135 1 0.8 150
// ... mixed with this:
// ../../bin/level_calc.py 2 150 7135 4 0.33 150 FET 1 10 1500
#define RAMP_LENGTH 150
#define PWM1_LEVELS 1,1,2,2,3,3,4,4,5,6,7,8,9,10,12,13,14,15,17,19,20,22,24,26,29,31,34,36,39,42,45,48,51,55,59,62,66,70,75,79,84,89,93,99,104,110,115,121,127,134,140,147,154,161,168,176,184,192,200,209,217,226,236,245,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0
#define PWM2_LEVELS 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,3,4,5,7,8,9,11,12,14,15,17,19,20,22,24,25,27,29,31,33,35,37,39,41,43,45,48,50,52,55,57,59,62,64,67,70,72,75,78,81,84,87,90,93,96,99,102,105,109,112,115,119,122,126,129,133,137,141,144,148,152,156,160,165,169,173,177,182,186,191,195,200,205,209,214,219,224,229,234,239,244,250,255
#define MAX_1x7135 65
#define HALFSPEED_LEVEL 14
#define QUARTERSPEED_LEVEL 5

// ceiling is level 120/150
#define RAMP_SMOOTH_CEIL (MAX_LEVEL*4/5)

// thermal regulation parameters
#ifdef MIN_THERM_STEPDOWN
#undef MIN_THERM_STEPDOWN  // this should be lower, because 3x7135 instead of 1x7135
#endif
#define MIN_THERM_STEPDOWN 60  // lowest value it'll step down to
#define THERM_FASTER_LEVEL (RAMP_SIZE*9/10)  // throttle back faster when high

fsm-adc.c

static inline uint8_t calc_voltage_divider(uint16_t value) {
    // use 10.6 fixed-point to get sufficient precision
    uint16_t adc_per_volt = ((ADC_44<<6) - (ADC_22<<6)) / (44-22);
    // incoming value is a 10-bit ADC reading (0..1024 = 0..1.1V), so shift it to match
    uint8_t result = ((value<<6) / adc_per_volt) + VOLTAGE_FUDGE_FACTOR;
    return result;
}

hwdef-Lexel_2S.h

#ifndef HWDEF_LEXEL_2S_H
#define HWDEF_LEXEL_2S_H

/* Lexel 2S Fet+1 driver layout
 *           ----
 *   Reset - PB5 |1  8|- VCC
 * eswitch - PB3 |2  7|- PB2 - Voltage divider
 *           PB4 |3  6|- PB1 - FET
 *          GND -|4  5|- PB0 - 1x7135
 *                ----
 */

#define LAYOUT_DEFINED

#define PWM_CHANNELS 2

#ifndef SWITCH_PIN
#define SWITCH_PIN   PB3    // pin 2
#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt
#endif

#ifndef PWM1_PIN
#define PWM1_PIN PB0        // pin 5, 1x7135 PWM
#define PWM1_LVL OCR0A      // OCR0A is the output compare register for PB0
#endif
#ifndef PWM2_PIN
#define PWM2_PIN PB1        // pin 6, FET PWM
#define PWM2_LVL OCR0B      // OCR0B is the output compare register for PB1
#endif

#define USE_VOLTAGE_DIVIDER // use a voltage divider on pin 7, not VCC
#ifndef VOLTAGE_PIN
#define VOLTAGE_PIN PB2     // pin 7, voltage ADC
#define VOLTAGE_CHANNEL 0x01 // MUX 01 corresponds with PB2
#define VOLTAGE_ADC_DIDR ADC1D  // Digital input disable bit corresponding with PB2
// 1.1V reference, left-adjust, ADC1/PB2
//#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | (1 << ADLAR) | VOLTAGE_CHANNEL)
// 1.1V reference, no left-adjust, ADC1/PB2
#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL)
#endif
#define ADC_PRSCL   0x06    // clk/64

#define VOLTAGE_FUDGE_FACTOR 0

// Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line)
#ifndef ADC_44
#define ADC_44 472
#endif
#ifndef ADC_22
#define ADC_22 236
#endif

#define TEMP_CHANNEL 0b00001111

#define FAST 0xA3           // fast PWM both channels
#define PHASE 0xA1          // phase-correct PWM both channels

#endif