verilog queue

queue.v

module queue(clk, trig, q, write_en);
   parameter BUFF_SIZE=20;

   input clk;
   input trig;
   output reg [7:0] q = 0;
   output reg write_en;

   reg [8*BUFF_SIZE:1] buff=0;
   reg [15:0]          buff_size = 0;
   reg [7:0]           out = 0;
   reg                 i=0;

   always @(posedge clk) begin
      if (trig == 1 && buff_size < BUFF_SIZE - 3) begin
         buff[8*(BUFF_SIZE-buff_size)-:3*8] <= "$SE";
         buff_size <= buff_size + 3;
         i <= 1;
      end
      q <= out;
      if (i == 1)
        write_en <= 1;
      if (buff_size == 0 && i == 0)
        write_en <= 0;
   end

   always @(negedge clk) begin
      if (buff_size > 0) begin
         buff <= {buff[8*BUFF_SIZE-8:1],8'b0};
         buff_size <= buff_size - 1;
         out <= buff[8*BUFF_SIZE:8*(BUFF_SIZE-1)+1];
      end
      if (buff_size == 0)
        i <= 0;
   end

endmodule

queue_tb.v

module queue_tb;
   reg clk;
   reg trig;
   wire [7:0] data;
   wire       write_en;

   queue queue1(clk,trig,data,write_en);

   initial begin
      clk = 0;
      forever begin
         #5 clk = ~clk;
      end
   end

   initial begin
      $monitor("data=%c,write_en=%d", data, write_en);
      trig = 0;
      #5 trig = 1;
      #20 trig = 0;
      #50 trig = 1;
      #55 trig = 0;
      #80 $finish;
   end

endmodule