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Created August 18, 2022 05:23
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Benchmarking masked AVX-512 memory ops
Raw
bench.sh
#!/bin/sh
echo "== Aligned load"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14" -asm "VMOVDQU8 zmm0, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8" -asm "VMOVDQU8 zmm0, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load (8b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VMOVDQU8 zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load (8b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VMOVDQU8 zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load (64b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VMOVDQU64 zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load (64b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VMOVDQU64 zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Aligned store"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14" -asm "VMOVDQU8 [rbx], zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8" -asm "VMOVDQU8 [rbx], zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store (8b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VMOVDQU8 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store (8b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VMOVDQU8 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store (64b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VMOVDQU64 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store (64b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VMOVDQU64 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Aligned load+store"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14" -asm "VMOVDQU8 zmm0, [rbx]; VMOVDQU8 [rbx], zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load+store"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8" -asm "VMOVDQU8 zmm0, [rbx]; VMOVDQU8 [rbx], zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load+store (8b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VMOVDQU8 zmm0{k1}{z}, [rbx]; VMOVDQU8 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load+store (8b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VMOVDQU8 zmm0{k1}{z}, [rbx]; VMOVDQU8 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load+store (64b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VMOVDQU64 zmm0{k1}{z}, [rbx]; VMOVDQU64 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load+store (64b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VMOVDQU64 zmm0{k1}{z}, [rbx]; VMOVDQU64 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Overlapping load+store"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14" -asm "VMOVDQU8 zmm0, [rbx-8]; VMOVDQU8 [rbx], zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Overlapping load+store (8b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; KXORQ k1, k1, k1" -asm "VMOVDQU8 zmm0{k1}{z}, [rbx-8]; VMOVDQU8 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Overlapping load+store (8b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; KXNORQ k1, k1, k1" -asm "VMOVDQU8 zmm0{k1}{z}, [rbx-8]; VMOVDQU8 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Overlapping load+store (64b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; KXORQ k1, k1, k1" -asm "VMOVDQU64 zmm0{k1}{z}, [rbx-8]; VMOVDQU64 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Overlapping load+store (64b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; KXNORQ k1, k1, k1" -asm "VMOVDQU64 zmm0{k1}{z}, [rbx-8]; VMOVDQU64 [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Aligned load-op"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14" -asm "VPADDB zmm0, zmm0, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-op"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8" -asm "VPADDB zmm0, zmm0, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-op (8b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VPADDB zmm0{k1}, zmm0, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-op (8b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VPADDB zmm0{k1}, zmm0, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-op (64b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VPADDQ zmm0{k1}, zmm0, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-op (64b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VPADDQ zmm0{k1}, zmm0, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Aligned load-expand (8b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; KXNORQ k1, k1, k1" -asm "VPEXPANDB zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-expand (8b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VPEXPANDB zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-expand (8b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VPEXPANDB zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-expand (64b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VPEXPANDQ zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-expand (64b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VPEXPANDQ zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Aligned store-compress (8b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; KXNORQ k1, k1, k1" -asm "VPCOMPRESSB [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store-compress (8b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VPCOMPRESSB [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store-compress (8b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VPCOMPRESSB [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store-compress (64b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VPCOMPRESSQ [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store-compress (64b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VPCOMPRESSQ [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Aligned load-expand (8->64b)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14" -asm "VPMOVZXBQ zmm0, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Aligned? load-expand (8->64b)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8" -asm "VPMOVZXBQ zmm0, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-expand (8->32b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VPMOVZXBD zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned load-expand (8->32b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VPMOVZXBD zmm0{k1}{z}, [rbx]" -config configs/cfg_AlderLakeP_common.txt
echo "== Aligned store-trunc (64->8b)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14" -asm "VPMOVQB [rbx], zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Aligned? store-trunc (64->8b)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8" -asm "VPMOVQB [rbx], zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store-trunc (64->16b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXORQ k1, k1, k1" -asm "VPMOVQW [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Unaligned store-trunc (64->16b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; KXNORQ k1, k1, k1" -asm "VPMOVQW [rbx]{k1}, zmm0" -config configs/cfg_AlderLakeP_common.txt
echo "== Gather same address (32b, 0 mask)"
./nanoBench.sh -asm_init "VPXORD zmm0, zmm0, zmm0; KXORQ k1, k1, k1" -asm "VPGATHERDD zmm1{k1}, [r14+zmm0]" -config configs/cfg_AlderLakeP_common.txt
echo "== Gather same address (32b, -1 mask)"
./nanoBench.sh -asm_init "VPXORD zmm0, zmm0, zmm0; KXNORQ k1, k1, k1" -asm "VPGATHERDD zmm1{k1}, [r14+zmm0]" -config configs/cfg_AlderLakeP_common.txt
echo "== Gather across two cachelines (32b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; MOV RAX, 8; VPBROADCASTQ ZMM0, RAX; KXORQ k1, k1, k1" -asm "VPGATHERDD zmm1{k1}, [rbx+zmm0]" -config configs/cfg_AlderLakeP_common.txt
echo "== Gather across two cachelines (32b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 8; MOV RAX, 8; VPBROADCASTQ ZMM0, RAX; KXNORQ k1, k1, k1" -asm "VPGATHERDD zmm1{k1}, [rbx+zmm0]" -config configs/cfg_AlderLakeP_common.txt
echo "== Gather across 32 cachelines (32b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 2; VPXORD ZMM0, ZMM0, ZMM0; MOV RAX, 128; VPINSRD XMM0, XMM0, EAX, 1; MOV RAX, 256; VPINSRD XMM0, XMM0, EAX, 2; MOV RAX, 384; VPINSRD XMM0, XMM0, EAX, 3; MOV RAX, 512; VPBROADCASTD XMM1, EAX; VPADDD XMM1, XMM1, XMM0; VINSERTI128 YMM0, YMM0, XMM1, 1; MOV RAX, 1024; VPBROADCASTD YMM1, EAX; VPADDD YMM1, YMM1, YMM0; VINSERTI32X8 ZMM0, ZMM0, YMM1, 1; KXORQ k1, k1, k1" -asm "VPGATHERDD zmm1{k1}, [rbx+zmm0]" -config configs/cfg_AlderLakeP_common.txt
echo "== Gather across 32 cachelines (32b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 2; VPXORD ZMM0, ZMM0, ZMM0; MOV RAX, 128; VPINSRD XMM0, XMM0, EAX, 1; MOV RAX, 256; VPINSRD XMM0, XMM0, EAX, 2; MOV RAX, 384; VPINSRD XMM0, XMM0, EAX, 3; MOV RAX, 512; VPBROADCASTD XMM1, EAX; VPADDD XMM1, XMM1, XMM0; VINSERTI128 YMM0, YMM0, XMM1, 1; MOV RAX, 1024; VPBROADCASTD YMM1, EAX; VPADDD YMM1, YMM1, YMM0; VINSERTI32X8 ZMM0, ZMM0, YMM1, 1; KXNORQ k1, k1, k1" -asm "VPGATHERDD zmm1{k1}, [rbx+zmm0]" -config configs/cfg_AlderLakeP_common.txt
echo "== Scatter same address (32b, 0 mask)"
./nanoBench.sh -asm_init "VPXORD zmm0, zmm0, zmm0; KXORQ k1, k1, k1" -asm "VPSCATTERDD [r14+zmm0]{k1}, zmm1" -config configs/cfg_AlderLakeP_common.txt
echo "== Scatter same address (32b, -1 mask)"
./nanoBench.sh -asm_init "VPXORD zmm0, zmm0, zmm0; KXNORQ k1, k1, k1" -asm "VPSCATTERDD [r14+zmm0]{k1}, zmm1" -config configs/cfg_AlderLakeP_common.txt
echo "== Scatter across 32 cachelines (32b, 0 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 2; VPXORD ZMM0, ZMM0, ZMM0; MOV RAX, 128; VPINSRD XMM0, XMM0, EAX, 1; MOV RAX, 256; VPINSRD XMM0, XMM0, EAX, 2; MOV RAX, 384; VPINSRD XMM0, XMM0, EAX, 3; MOV RAX, 512; VPBROADCASTD XMM1, EAX; VPADDD XMM1, XMM1, XMM0; VINSERTI128 YMM0, YMM0, XMM1, 1; MOV RAX, 1024; VPBROADCASTD YMM1, EAX; VPADDD YMM1, YMM1, YMM0; VINSERTI32X8 ZMM0, ZMM0, YMM1, 1; KXORQ k1, k1, k1" -asm "VPSCATTERDD [rbx+zmm0]{k1}, zmm1" -config configs/cfg_AlderLakeP_common.txt
echo "== Scatter across 32 cachelines (32b, -1 mask)"
./nanoBench.sh -asm_init "MOV RAX, 0x3f; ANDN RBX, RAX, R14; SUB RBX, 2; VPXORD ZMM0, ZMM0, ZMM0; MOV RAX, 128; VPINSRD XMM0, XMM0, EAX, 1; MOV RAX, 256; VPINSRD XMM0, XMM0, EAX, 2; MOV RAX, 384; VPINSRD XMM0, XMM0, EAX, 3; MOV RAX, 512; VPBROADCASTD XMM1, EAX; VPADDD XMM1, XMM1, XMM0; VINSERTI128 YMM0, YMM0, XMM1, 1; MOV RAX, 1024; VPBROADCASTD YMM1, EAX; VPADDD YMM1, YMM1, YMM0; VINSERTI32X8 ZMM0, ZMM0, YMM1, 1; KXNORQ k1, k1, k1" -asm "VPSCATTERDD [rbx+zmm0]{k1}, zmm1" -config configs/cfg_AlderLakeP_common.txt
Raw
results.csv
Aligned load Unaligned load Unaligned load (8b, 0 mask) Unaligned load (8b, -1 mask) Unaligned load (64b, 0 mask) Unaligned load (64b, -1 mask) Aligned store Unaligned store Unaligned store (8b, 0 mask) Unaligned store (8b, -1 mask) Unaligned store (64b, 0 mask) Unaligned store (64b, -1 mask) Aligned load+store Unaligned load+store Unaligned load+store (8b, 0 mask) Unaligned load+store (8b, -1 mask) Unaligned load+store (64b, 0 mask) Unaligned load+store (64b, -1 mask) Overlapping load+store Overlapping load+store (8b, 0 mask) Overlapping load+store (8b, -1 mask) Overlapping load+store (64b, 0 mask) Overlapping load+store (64b, -1 mask) Aligned load-op Unaligned load-op Unaligned load-op (8b, 0 mask) Unaligned load-op (8b, -1 mask) Unaligned load-op (64b, 0 mask) Unaligned load-op (64b, -1 mask) Aligned load-expand (8b, -1 mask) Unaligned load-expand (8b, 0 mask) Unaligned load-expand (8b, -1 mask) Unaligned load-expand (64b, 0 mask) Unaligned load-expand (64b, -1 mask) Aligned store-compress (8b, -1 mask) Unaligned store-compress (8b, 0 mask) Unaligned store-compress (8b, -1 mask) Unaligned store-compress (64b, 0 mask) Unaligned store-compress (64b, -1 mask) Aligned load-expand (8->64b) Aligned? load-expand (8->64b) Unaligned load-expand (8->32b, 0 mask) Unaligned load-expand (8->32b, -1 mask) Aligned store-trunc (64->8b) Aligned? store-trunc (64->8b) Unaligned store-trunc (64->16b, 0 mask) Unaligned store-trunc (64->16b, -1 mask) Gather same address (32b, 0 mask) Gather same address (32b, -1 mask) Gather across two cachelines (32b, 0 mask) Gather across two cachelines (32b, -1 mask) Gather across 32 cachelines (32b, 0 mask) Gather across 32 cachelines (32b, -1 mask) Scatter same address (32b, 0 mask) Scatter same address (32b, -1 mask) Scatter across 32 cachelines (32b, 0 mask) Scatter across 32 cachelines (32b, -1 mask)
CORE_CYCLES 0.34 3.14 2.91 2.76 2.59 2.53 1.00 24.00 24.00 25.00 23.00 24.00 6.99 41.00 46.47 47.47 40.79 45.65 25.00 29.49 29.49 27.01 26.98 1.00 2.97 3.01 2.98 3.03 2.96 2.00 2.30 2.24 2.36 2.28 6.00 24.00 25.00 23.00 24.00 1.00 1.00 3.19 3.25 2.00 2.00 23.00 24.00 5.77 5.75 5.75 5.75 5.75 5.75 11.01 11.00 11.00 11.00
INST_RETIRED 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00
IDQ.MITE_UOPS 1.01 1.01 1.00 1.01 1.01 1.00 1.00 0.99 3.99 4.01 1.00 1.01 2.02 2.01 5.00 5.00 2.00 2.00 2.04 5.03 5.04 2.04 2.04 0.99 1.00 1.00 1.01 1.01 1.00 2.00 2.00 2.00 1.99 2.02 4.00 4.02 3.99 2.99 2.99 2.04 2.00 2.00 2.01 3.00 3.00 3.00 3.00 5.00 4.99 5.00 4.99 5.00 5.00 4.00 3.99 4.01 4.00
IDQ.DSB_UOPS -0.02 -0.01 0.01 0.00 -0.01 0.01 -0.02 0.02 0.02 -0.02 -0.02 0.00 0.00 -0.01 -0.02 0.00 0.00 0.00 -0.06 -0.06 -0.06 -0.06 -0.06 0.00 0.00 0.00 0.02 0.02 0.00 0.03 -0.01 0.00 -0.02 0.00 0.01 -0.01 -0.01 -0.01 -0.01 -0.02 0.00 0.00 -0.01 0.00 0.00 0.00 0.00 0.00 0.02 0.00 0.01 0.00 0.00 0.01 0.02 -0.01 0.00
IDQ.MS_UOPS 0.00 -0.01 0.02 0.01 0.02 0.01 0.00 -0.02 0.02 0.02 0.00 0.00 0.00 0.04 0.02 0.02 0.00 0.03 0.06 0.03 0.03 0.05 0.05 0.00 0.01 -0.03 0.01 0.02 0.00 0.00 0.01 -0.01 0.00 0.00 4.00 3.96 3.95 0.00 0.00 0.03 0.00 0.00 -0.02 0.00 0.00 -0.01 0.02 0.00 0.03 0.01 0.02 0.03 0.04 32.00 32.00 32.00 32.00
LSD.UOPS 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
UOPS_ISSUED 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 4.00 4.00 1.00 1.00 2.00 2.00 5.00 5.00 2.00 2.00 2.01 5.01 5.01 2.01 2.01 1.00 1.00 1.00 1.00 1.00 1.00 2.00 2.00 2.00 2.00 2.00 8.00 8.00 8.00 3.00 3.00 2.00 2.00 2.00 2.00 3.00 3.00 3.00 3.00 5.00 5.00 5.00 5.00 5.00 5.00 36.00 36.00 36.00 36.00
UOPS_EXECUTED 1.00 1.00 2.00 2.00 2.00 2.00 2.00 2.00 5.00 5.00 2.00 2.00 3.00 3.00 7.00 7.00 4.00 4.00 3.01 7.01 7.00 4.01 4.01 2.00 2.00 2.00 2.00 2.00 2.00 3.00 3.00 3.00 3.00 3.00 8.00 8.00 8.00 4.00 4.00 2.00 2.00 2.00 2.00 4.00 4.00 4.00 4.00 6.00 6.00 6.00 6.00 6.00 6.00 35.00 35.00 35.00 35.00
UOPS_RETIRED.SLOTS 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 4.00 4.00 1.00 1.00 2.00 2.00 5.00 5.00 2.00 2.00 2.01 5.01 5.01 2.01 2.01 1.00 1.00 1.00 1.00 1.00 1.00 2.00 2.00 2.00 2.00 2.00 8.00 8.00 8.00 3.00 3.00 2.00 2.00 2.00 2.00 3.00 3.00 3.00 3.00 5.00 5.00 5.00 5.00 5.00 5.00 36.00 36.00 36.00 36.00
UOPS_DISPATCHED_PORT.PORT_0 0.00 0.00 0.50 0.50 2.10 2.19 0.00 0.00 0.33 0.33 0.00 0.00 0.00 0.00 0.49 0.49 2.01 2.06 0.00 0.49 0.49 1.54 1.54 0.50 0.56 0.50 0.50 0.58 0.59 0.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00 1.00 1.00 2.00 2.00 2.00 2.00
UOPS_DISPATCHED_PORT.PORT_1 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.17 0.17 0.00 0.00 0.00 0.17 0.17 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.50 1.00 1.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10 1.00 1.00 1.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00 16.00 16.00 16.00 16.00 16.00 16.00 0.00 0.00 0.00 0.00
UOPS_DISPATCHED_PORT.PORT_4_9 0.00 0.00 0.00 0.00 0.00 0.00 1.00 1.00 2.00 2.00 1.00 1.00 4.57 3.33 2.00 2.00 1.00 1.00 3.33 2.00 2.00 1.00 1.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.00 2.00 2.00 1.00 1.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00 0.00 0.00 16.00 16.00 16.00 16.00
UOPS_DISPATCHED_PORT.PORT_5_11 0.00 0.00 0.49 0.51 2.12 2.12 0.00 0.00 0.67 0.67 0.00 0.00 0.00 0.00 1.18 1.18 1.35 1.64 0.00 1.17 1.17 1.56 1.57 0.50 0.58 0.50 0.50 0.59 0.58 2.00 2.00 2.00 3.02 3.01 2.00 2.00 2.00 2.00 2.00 1.00 1.00 3.04 3.03 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 0.00 0.00 0.00 0.00
UOPS_DISPATCHED_PORT.PORT_6 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.16 0.16 0.00 0.00 0.00 0.19 0.19 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.50 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00
UOPS_DISPATCHED_PORT.PORT_7_8 0.00 0.00 0.00 0.00 0.00 0.00 1.00 1.00 2.00 2.00 1.00 1.00 1.00 1.00 2.00 2.00 1.00 1.00 1.00 2.00 2.00 1.00 1.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.00 2.00 2.00 1.00 1.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00 0.00 0.00 16.00 16.00 16.00 16.00
BR_INST_RETIRED.ALL_BRANCHES 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
BR_MISP_RETIRED.ALL_BRANCHES 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
MEM_LOAD_RETIRED.L1_HIT 1.00 1.00 1.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00
MEM_LOAD_RETIRED.L1_MISS 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
MEM_LOAD_RETIRED.L2_HIT 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
MEM_LOAD_RETIRED.L2_MISS 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
MEM_LOAD_RETIRED.L3_HIT 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
MEM_LOAD_RETIRED.L3_MISS 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
Raw
results.txt
== Aligned load
CORE_CYCLES: 0.34
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.01
IDQ.DSB_UOPS: -0.02
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 1.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load
CORE_CYCLES: 3.14
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.01
IDQ.DSB_UOPS: -0.01
IDQ.MS_UOPS: -0.01
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 1.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load (8b, 0 mask)
CORE_CYCLES: 2.91
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.00
IDQ.DSB_UOPS: 0.01
IDQ.MS_UOPS: 0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.50
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.49
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load (8b, -1 mask)
CORE_CYCLES: 2.76
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.01
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.01
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.50
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.51
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load (64b, 0 mask)
CORE_CYCLES: 2.59
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.01
IDQ.DSB_UOPS: -0.01
IDQ.MS_UOPS: 0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 2.10
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.12
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load (64b, -1 mask)
CORE_CYCLES: 2.53
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.00
IDQ.DSB_UOPS: 0.01
IDQ.MS_UOPS: 0.01
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 2.19
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.12
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Aligned store
CORE_CYCLES: 1.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.00
IDQ.DSB_UOPS: -0.02
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store
CORE_CYCLES: 24.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 0.99
IDQ.DSB_UOPS: 0.02
IDQ.MS_UOPS: -0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store (8b, 0 mask)
CORE_CYCLES: 24.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 3.99
IDQ.DSB_UOPS: 0.02
IDQ.MS_UOPS: 0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 4.00
UOPS_EXECUTED: 5.00
UOPS_RETIRED.SLOTS: 4.00
UOPS_DISPATCHED_PORT.PORT_0: 0.33
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 2.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.67
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 2.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store (8b, -1 mask)
CORE_CYCLES: 25.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 4.01
IDQ.DSB_UOPS: -0.02
IDQ.MS_UOPS: 0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 4.00
UOPS_EXECUTED: 5.00
UOPS_RETIRED.SLOTS: 4.00
UOPS_DISPATCHED_PORT.PORT_0: 0.33
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 2.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.67
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 2.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store (64b, 0 mask)
CORE_CYCLES: 23.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.00
IDQ.DSB_UOPS: -0.02
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store (64b, -1 mask)
CORE_CYCLES: 24.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.01
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Aligned load+store
CORE_CYCLES: 6.99
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 2.02
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 3.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 4.57
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load+store
CORE_CYCLES: 41.00
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 2.01
IDQ.DSB_UOPS: -0.01
IDQ.MS_UOPS: 0.04
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 3.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 3.33
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load+store (8b, 0 mask)
CORE_CYCLES: 46.47
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 5.00
IDQ.DSB_UOPS: -0.02
IDQ.MS_UOPS: 0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 5.00
UOPS_EXECUTED: 7.00
UOPS_RETIRED.SLOTS: 5.00
UOPS_DISPATCHED_PORT.PORT_0: 0.49
UOPS_DISPATCHED_PORT.PORT_1: 0.17
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 2.00
UOPS_DISPATCHED_PORT.PORT_5_11: 1.18
UOPS_DISPATCHED_PORT.PORT_6: 0.16
UOPS_DISPATCHED_PORT.PORT_7_8: 2.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load+store (8b, -1 mask)
CORE_CYCLES: 47.47
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 5.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 5.00
UOPS_EXECUTED: 7.00
UOPS_RETIRED.SLOTS: 5.00
UOPS_DISPATCHED_PORT.PORT_0: 0.49
UOPS_DISPATCHED_PORT.PORT_1: 0.17
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 2.00
UOPS_DISPATCHED_PORT.PORT_5_11: 1.18
UOPS_DISPATCHED_PORT.PORT_6: 0.16
UOPS_DISPATCHED_PORT.PORT_7_8: 2.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load+store (64b, 0 mask)
CORE_CYCLES: 40.79
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 2.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 4.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 2.01
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 1.35
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load+store (64b, -1 mask)
CORE_CYCLES: 45.65
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 2.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.03
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 4.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 2.06
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 1.64
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Overlapping load+store
CORE_CYCLES: 25.00
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 2.04
IDQ.DSB_UOPS: -0.06
IDQ.MS_UOPS: 0.06
LSD.UOPS: 0.00
UOPS_ISSUED: 2.01
UOPS_EXECUTED: 3.01
UOPS_RETIRED.SLOTS: 2.01
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 3.33
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Overlapping load+store (8b, 0 mask)
CORE_CYCLES: 29.49
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 5.03
IDQ.DSB_UOPS: -0.06
IDQ.MS_UOPS: 0.03
LSD.UOPS: 0.00
UOPS_ISSUED: 5.01
UOPS_EXECUTED: 7.01
UOPS_RETIRED.SLOTS: 5.01
UOPS_DISPATCHED_PORT.PORT_0: 0.49
UOPS_DISPATCHED_PORT.PORT_1: 0.17
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 2.00
UOPS_DISPATCHED_PORT.PORT_5_11: 1.17
UOPS_DISPATCHED_PORT.PORT_6: 0.19
UOPS_DISPATCHED_PORT.PORT_7_8: 2.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Overlapping load+store (8b, -1 mask)
CORE_CYCLES: 29.49
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 5.04
IDQ.DSB_UOPS: -0.06
IDQ.MS_UOPS: 0.03
LSD.UOPS: 0.00
UOPS_ISSUED: 5.01
UOPS_EXECUTED: 7.00
UOPS_RETIRED.SLOTS: 5.01
UOPS_DISPATCHED_PORT.PORT_0: 0.49
UOPS_DISPATCHED_PORT.PORT_1: 0.17
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 2.00
UOPS_DISPATCHED_PORT.PORT_5_11: 1.17
UOPS_DISPATCHED_PORT.PORT_6: 0.19
UOPS_DISPATCHED_PORT.PORT_7_8: 2.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Overlapping load+store (64b, 0 mask)
CORE_CYCLES: 27.01
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 2.04
IDQ.DSB_UOPS: -0.06
IDQ.MS_UOPS: 0.05
LSD.UOPS: 0.00
UOPS_ISSUED: 2.01
UOPS_EXECUTED: 4.01
UOPS_RETIRED.SLOTS: 2.01
UOPS_DISPATCHED_PORT.PORT_0: 1.54
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 1.56
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Overlapping load+store (64b, -1 mask)
CORE_CYCLES: 26.98
INST_RETIRED: 2.00
IDQ.MITE_UOPS: 2.04
IDQ.DSB_UOPS: -0.06
IDQ.MS_UOPS: 0.05
LSD.UOPS: 0.00
UOPS_ISSUED: 2.01
UOPS_EXECUTED: 4.01
UOPS_RETIRED.SLOTS: 2.01
UOPS_DISPATCHED_PORT.PORT_0: 1.54
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 1.57
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Aligned load-op
CORE_CYCLES: 1.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 0.99
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.50
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.50
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-op
CORE_CYCLES: 2.97
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.01
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.56
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.58
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-op (8b, 0 mask)
CORE_CYCLES: 3.01
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: -0.03
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.50
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.50
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-op (8b, -1 mask)
CORE_CYCLES: 2.98
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.01
IDQ.DSB_UOPS: 0.02
IDQ.MS_UOPS: 0.01
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.50
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.50
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-op (64b, 0 mask)
CORE_CYCLES: 3.03
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.01
IDQ.DSB_UOPS: 0.02
IDQ.MS_UOPS: 0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.58
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.59
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-op (64b, -1 mask)
CORE_CYCLES: 2.96
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 1.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 1.00
UOPS_DISPATCHED_PORT.PORT_0: 0.59
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.58
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Aligned load-expand (8b, -1 mask)
CORE_CYCLES: 2.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 2.00
IDQ.DSB_UOPS: 0.03
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 3.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-expand (8b, 0 mask)
CORE_CYCLES: 2.30
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 2.00
IDQ.DSB_UOPS: -0.01
IDQ.MS_UOPS: 0.01
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 3.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-expand (8b, -1 mask)
CORE_CYCLES: 2.24
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 2.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: -0.01
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 3.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-expand (64b, 0 mask)
CORE_CYCLES: 2.36
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 1.99
IDQ.DSB_UOPS: -0.02
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 3.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 3.02
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-expand (64b, -1 mask)
CORE_CYCLES: 2.28
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 2.02
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 3.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 3.01
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Aligned store-compress (8b, -1 mask)
CORE_CYCLES: 6.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 4.00
IDQ.DSB_UOPS: 0.01
IDQ.MS_UOPS: 4.00
LSD.UOPS: 0.00
UOPS_ISSUED: 8.00
UOPS_EXECUTED: 8.00
UOPS_RETIRED.SLOTS: 8.00
UOPS_DISPATCHED_PORT.PORT_0: 1.00
UOPS_DISPATCHED_PORT.PORT_1: 0.50
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 2.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.50
UOPS_DISPATCHED_PORT.PORT_7_8: 2.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store-compress (8b, 0 mask)
CORE_CYCLES: 24.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 4.02
IDQ.DSB_UOPS: -0.01
IDQ.MS_UOPS: 3.96
LSD.UOPS: 0.00
UOPS_ISSUED: 8.00
UOPS_EXECUTED: 8.00
UOPS_RETIRED.SLOTS: 8.00
UOPS_DISPATCHED_PORT.PORT_0: 1.00
UOPS_DISPATCHED_PORT.PORT_1: 1.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 2.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 2.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store-compress (8b, -1 mask)
CORE_CYCLES: 25.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 3.99
IDQ.DSB_UOPS: -0.01
IDQ.MS_UOPS: 3.95
LSD.UOPS: 0.00
UOPS_ISSUED: 8.00
UOPS_EXECUTED: 8.00
UOPS_RETIRED.SLOTS: 8.00
UOPS_DISPATCHED_PORT.PORT_0: 1.00
UOPS_DISPATCHED_PORT.PORT_1: 1.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 2.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 2.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store-compress (64b, 0 mask)
CORE_CYCLES: 23.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 2.99
IDQ.DSB_UOPS: -0.01
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 3.00
UOPS_EXECUTED: 4.00
UOPS_RETIRED.SLOTS: 3.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store-compress (64b, -1 mask)
CORE_CYCLES: 24.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 2.99
IDQ.DSB_UOPS: -0.01
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 3.00
UOPS_EXECUTED: 4.00
UOPS_RETIRED.SLOTS: 3.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Aligned load-expand (8->64b)
CORE_CYCLES: 1.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 2.04
IDQ.DSB_UOPS: -0.02
IDQ.MS_UOPS: 0.03
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 1.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Aligned? load-expand (8->64b)
CORE_CYCLES: 1.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 2.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 1.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-expand (8->32b, 0 mask)
CORE_CYCLES: 3.19
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 2.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 3.04
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned load-expand (8->32b, -1 mask)
CORE_CYCLES: 3.25
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 2.01
IDQ.DSB_UOPS: -0.01
IDQ.MS_UOPS: -0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 2.00
UOPS_EXECUTED: 2.00
UOPS_RETIRED.SLOTS: 2.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 1.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 3.03
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Aligned store-trunc (64->8b)
CORE_CYCLES: 2.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 3.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 3.00
UOPS_EXECUTED: 4.00
UOPS_RETIRED.SLOTS: 3.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Aligned? store-trunc (64->8b)
CORE_CYCLES: 2.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 3.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 3.00
UOPS_EXECUTED: 4.00
UOPS_RETIRED.SLOTS: 3.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store-trunc (64->16b, 0 mask)
CORE_CYCLES: 23.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 3.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: -0.01
LSD.UOPS: 0.00
UOPS_ISSUED: 3.00
UOPS_EXECUTED: 4.00
UOPS_RETIRED.SLOTS: 3.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Unaligned store-trunc (64->16b, -1 mask)
CORE_CYCLES: 24.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 3.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 3.00
UOPS_EXECUTED: 4.00
UOPS_RETIRED.SLOTS: 3.00
UOPS_DISPATCHED_PORT.PORT_0: 0.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 1.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 1.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Gather same address (32b, 0 mask)
CORE_CYCLES: 5.77
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 5.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.00
LSD.UOPS: 0.00
UOPS_ISSUED: 5.00
UOPS_EXECUTED: 6.00
UOPS_RETIRED.SLOTS: 5.00
UOPS_DISPATCHED_PORT.PORT_0: 1.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 16.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Gather same address (32b, -1 mask)
CORE_CYCLES: 5.75
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 4.99
IDQ.DSB_UOPS: 0.02
IDQ.MS_UOPS: 0.03
LSD.UOPS: 0.00
UOPS_ISSUED: 5.00
UOPS_EXECUTED: 6.00
UOPS_RETIRED.SLOTS: 5.00
UOPS_DISPATCHED_PORT.PORT_0: 1.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 16.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Gather across two cachelines (32b, 0 mask)
CORE_CYCLES: 5.75
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 5.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.01
LSD.UOPS: 0.00
UOPS_ISSUED: 5.00
UOPS_EXECUTED: 6.00
UOPS_RETIRED.SLOTS: 5.00
UOPS_DISPATCHED_PORT.PORT_0: 1.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 16.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Gather across two cachelines (32b, -1 mask)
CORE_CYCLES: 5.75
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 4.99
IDQ.DSB_UOPS: 0.01
IDQ.MS_UOPS: 0.02
LSD.UOPS: 0.00
UOPS_ISSUED: 5.00
UOPS_EXECUTED: 6.00
UOPS_RETIRED.SLOTS: 5.00
UOPS_DISPATCHED_PORT.PORT_0: 1.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 16.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Gather across 32 cachelines (32b, 0 mask)
CORE_CYCLES: 5.75
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 5.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.03
LSD.UOPS: 0.00
UOPS_ISSUED: 5.00
UOPS_EXECUTED: 6.00
UOPS_RETIRED.SLOTS: 5.00
UOPS_DISPATCHED_PORT.PORT_0: 1.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 16.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Gather across 32 cachelines (32b, -1 mask)
CORE_CYCLES: 5.75
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 5.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 0.04
LSD.UOPS: 0.00
UOPS_ISSUED: 5.00
UOPS_EXECUTED: 6.00
UOPS_RETIRED.SLOTS: 5.00
UOPS_DISPATCHED_PORT.PORT_0: 1.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 16.00
UOPS_DISPATCHED_PORT.PORT_4_9: 0.00
UOPS_DISPATCHED_PORT.PORT_5_11: 2.00
UOPS_DISPATCHED_PORT.PORT_6: 0.00
UOPS_DISPATCHED_PORT.PORT_7_8: 0.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 1.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Scatter same address (32b, 0 mask)
CORE_CYCLES: 11.01
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 4.00
IDQ.DSB_UOPS: 0.01
IDQ.MS_UOPS: 32.00
LSD.UOPS: 0.00
UOPS_ISSUED: 36.00
UOPS_EXECUTED: 35.00
UOPS_RETIRED.SLOTS: 36.00
UOPS_DISPATCHED_PORT.PORT_0: 2.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 16.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 1.00
UOPS_DISPATCHED_PORT.PORT_7_8: 16.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Scatter same address (32b, -1 mask)
CORE_CYCLES: 11.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 3.99
IDQ.DSB_UOPS: 0.02
IDQ.MS_UOPS: 32.00
LSD.UOPS: 0.00
UOPS_ISSUED: 36.00
UOPS_EXECUTED: 35.00
UOPS_RETIRED.SLOTS: 36.00
UOPS_DISPATCHED_PORT.PORT_0: 2.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 16.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 1.00
UOPS_DISPATCHED_PORT.PORT_7_8: 16.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Scatter across 32 cachelines (32b, 0 mask)
CORE_CYCLES: 11.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 4.01
IDQ.DSB_UOPS: -0.01
IDQ.MS_UOPS: 32.00
LSD.UOPS: 0.00
UOPS_ISSUED: 36.00
UOPS_EXECUTED: 35.00
UOPS_RETIRED.SLOTS: 36.00
UOPS_DISPATCHED_PORT.PORT_0: 2.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 16.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 1.00
UOPS_DISPATCHED_PORT.PORT_7_8: 16.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
== Scatter across 32 cachelines (32b, -1 mask)
CORE_CYCLES: 11.00
INST_RETIRED: 1.00
IDQ.MITE_UOPS: 4.00
IDQ.DSB_UOPS: 0.00
IDQ.MS_UOPS: 32.00
LSD.UOPS: 0.00
UOPS_ISSUED: 36.00
UOPS_EXECUTED: 35.00
UOPS_RETIRED.SLOTS: 36.00
UOPS_DISPATCHED_PORT.PORT_0: 2.00
UOPS_DISPATCHED_PORT.PORT_1: 0.00
UOPS_DISPATCHED_PORT.PORT_2_3_10: 0.00
UOPS_DISPATCHED_PORT.PORT_4_9: 16.00
UOPS_DISPATCHED_PORT.PORT_5_11: 0.00
UOPS_DISPATCHED_PORT.PORT_6: 1.00
UOPS_DISPATCHED_PORT.PORT_7_8: 16.00
BR_INST_RETIRED.ALL_BRANCHES: 0.00
BR_MISP_RETIRED.ALL_BRANCHES: 0.00
MEM_LOAD_RETIRED.L1_HIT: 0.00
MEM_LOAD_RETIRED.L1_MISS: 0.00
MEM_LOAD_RETIRED.L2_HIT: 0.00
MEM_LOAD_RETIRED.L2_MISS: 0.00
MEM_LOAD_RETIRED.L3_HIT: 0.00
MEM_LOAD_RETIRED.L3_MISS: 0.00
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