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173210/vfpu.c

Created August 19, 2016 23:44
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[WIP] VFPU instructions
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vfpu.c
{"bvf", "?B,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, AL, 0, 0 },
{"bvfl", "?B,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, AL, 0, 0 },
{"bvt", "?B,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, AL, 0, 0 },
{"bvtl", "?B,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, AL, 0, 0 },
{"lv.s", "?$,o(b)", 0, (int) M_LV_Q_OB, INSN_MACRO, 0, AL, 0, 0 },
{"lv.s", "?$,A(b)", 0, (int) M_LV_Q_AB, INSN_MACRO, 0, AL, 0, 0 },
{"lv.s", "?D(b)", 0xc8000000, 0xfc000000, CLD|RD_1|WR_CC, 0, AL, 0, 0 },
{"ulv.s", "?$,o(b)", 0, (int) M_ULV_S, INSN_MACRO, 0, AL, 0, 0 },
{"lv.q", "?/,o(b)", 0, (int) M_LV_Q_OB_2, INSN_MACRO, 0, AL, 0, 0 },
{"lv.q", "?/,A(b)", 0, (int) M_LV_Q_AB_2, INSN_MACRO, 0, AL, 0, 0 },
{"lv.q", "?D(b)", 0xd8000000, 0xfc000002, CLD|RD_1|WR_CC, 0, AL, 0, 0 },
{"ulv.q", "?D(b)", 0, (int) M_ULV_Q, INSN_MACRO, 0, AL, 0, 0 },
{"ulv.q", "?/,A(b)", 0, (int) M_ULV_Q_AB, INSN_MACRO, 0, AL, 0, 0 },
{"lvi.s", "?$,l?y0", 0, (int) M_LVI_S, INSN_MACRO, 0, AL, 0, 0 },
{"lvi.p", "?(,?[l?y0,l?y1?]", 0, (int) M_LVI_P, INSN_MACRO, 0, AL, 0, 0 },
{"lvi.t", "?+,?[l?y0,l?y1,l?y2?]", 0, (int) M_LVI_T, INSN_MACRO, 0, AL, 0, 0 },
{"lvi.q", "?/,?[l?y0,l?y1,l?y2,l?y3?]", 0, (int) M_LVI_Q, INSN_MACRO, 0, AL, 0, 0 },
{"lvhi.s", "?$,?[?u?y0,?u?y1?]", 0, (int) M_LVHI_S, INSN_MACRO, 0, AL, 0, 0 },
{"lvhi.p", "?(,?[?u?y0,?u?y1,?u?y2,?u?y3?]", 0, (int) M_LVHI_P, INSN_MACRO, 0, AL, 0, 0 },
{"sv.s", "?!,o(b)", 0, (int) M_SV_S_OB, INSN_MACRO, 0, AL, 0, 0 },
{"sv.s", "?!,A(b)", 0, (int) M_SV_S_AB, INSN_MACRO, 0, AL, 0, 0 },
{"sv.s", "?D(b)", 0xe8000000, 0xfc000000, SM|RD_1|RD_C2, 0, AL, 0, 0 },
{"usv.s", "?!,o(b)", 0, (int) M_USV_S, INSN_MACRO, 0, AL, 0, 0 },
{"sv.q", "?-,o(b)", 0, (int) M_SV_Q_OB, INSN_MACRO, 0, AL, 0, 0 },
{"sv.q", "?-,o(b),?r", 0, (int) M_SV_Q_OB, INSN_MACRO, 0, AL, 0, 0 },
{"sv.q", "?-,A(b)", 0, (int) M_SV_Q_AB, INSN_MACRO, 0, AL, 0, 0 },
{"sv.q", "?-,A(b),?r", 0, (int) M_SV_Q_AB, INSN_MACRO, 0, AL, 0, 0 },
{"sv.q", "?-,A,?r", 0, (int) M_SV_Q_AB, INSN_MACRO, 0, AL, 0, 0 },
{"sv.q", "?D(b)", 0xf8000000, 0xfc000002, SM|RD_1|RD_C2, 0, AL, 0, 0 },
{"sv.q", "?D(b),?r", 0xf8000000, 0xfc000000, SM|RD_1|RD_C2, 0, AL, 0, 0 },
{"usv.q", "?-,o(b)", 0, (int) M_USV_Q, INSN_MACRO, 0, AL, 0, 0 },
{"usv.q", "?-,A(b)", 0, (int) M_USV_Q_AB, INSN_MACRO, 0, AL, 0, 0 },
{"vwb.q", "?-,o(b)", 0, (int) M_VWB_Q, SM|RD_1|RD_C2, 0, AL, 0, 0 },
{"vwb.q", "?D(b)", 0xf8000002, 0xfc000002, SM|RD_1|RD_C2, 0, AL, 0, 0 },
{"lvl.q", "?-,o(b)", 0, (int) M_LVL_Q_OB, CLD|RD_1|WR_CC, 0, AL, 0, 0 },
{"lvl.q", "?-,A(b)", 0, (int) M_LVL_Q_AB, INSN_MACRO, 0, AL, 0, 0 },
{"lvl.q", "?D(b)", 0xd4000000, 0xfc000002, CLD|RD_1|WR_CC, 0, AL, 0, 0 },
{"lvr.q", "?-,o(b)", 0, (int) M_LVR_Q_OB, INSN_MACRO, 0, AL, 0, 0 },
{"lvr.q", "?-,A(b)", 0, (int) M_LVR_Q_AB, INSN_MACRO, 0, AL, 0, 0 },
{"lvr.q", "?D(b)", 0xd4000002, 0xfc000002, CLD|RD_1|WR_CC, 0, AL, 0, 0 },
{"svl.q", "?-,o(b)", 0, (int) M_SVL_Q_OB, INSN_MACRO, 0, AL, 0, 0 },
{"svl.q", "?-,A(b)", 0, (int) M_SVL_Q_AB, INSN_MACRO, 0, AL, 0, 0 },
{"svl.q", "?D(b)", 0xf4000000, 0xfc000002, SM|RD_1|RD_C2, 0, AL, 0, 0 },
{"svr.q", "?-,o(b)", 0, (int) M_SVR_Q_OB, INSN_MACRO, 0, AL, 0, 0 },
{"svr.q", "?-,A(b)", 0, (int) M_SVR_Q_AB, INSN_MACRO, 0, AL, 0, 0 },
{"svr.q", "?D(b)", 0xf4000002, 0xfc000002, SM|RD_1|RD_C2, 0, AL, 0, 0 },
{"mtv", "t,?$", 0x48e00000, 0xffe0ff80, LC|WR_1|WR_C2, 0, AL, 0, 0 },
{"mfv", "t,?$", 0x48600000, 0xffe0ff80, CM|RD_2|WR_CC|RD_C2, 0, AL, 0, 0 },
{"mtvc", "t,?C", 0x48e00000, 0xffe0ff00, LC|WR_1|WR_C2, 0, AL, 0, 0 },
{"mfvc", "t,?C", 0x48600000, 0xffe0ff00, CM|RD_2|WR_CC|RD_C2, 0, AL, 0, 0 },
{"vmtvc", "?C,?!", 0xd0510000, 0xffff8000, WR_C2, 0, AL, 0, 0 },
{"vmfvc", "?$,?c", 0xd0500000, 0xffff0080, RD_C2, 0, AL, 0, 0 },
{"vadd", "?2p,?0P,?1P", 0, (int) M_VFPU_D_S_T, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vadd", "?2,?0,?1", 0x60000000, 0xff808080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsub", "?2p,?0P,?1P", 0, (int) M_VFPU_D_S_T, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsub", "?2,?0,?1", 0x60800000, 0xff808080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vdiv", "?2p,?0P,?1P", 0, (int) M_VFPU_D_S_T, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vdiv", "?2,?0,?1", 0x63800000, 0xff808080, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vmul", "?2p,?0P,?1P", 0, (int) M_VFPU_D_S_T, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vmul", "?2,?0,?1", 0x64000000, 0xff808080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vdot", "?$p,?0P,?1P", 0, (int) M_VFPU_D1_S_T, INSN_MACRO, VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vdot", "?$,?0,?1", 0x64800000, 0xff808080, RD_C2, VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vscl", "?2p,?0P,?#", 0, (int) M_VFPU_D_S_T1, INSN_MACRO, VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vscl", "?2,?0,?#", 0x65000000, 0xff808080, RD_C2, VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vhdp", "?$p,?0P,?1P", 0, (int) M_VFPU_D1_SP_T, INSN_MACRO, VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vhdp", "?$,?0,?1", 0x66000000, 0xff808080, RD_C2, VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcmp", "?F,?0P,?1P", 0, (int) M_VFPU_C_S_T, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcmp", "?F,?0,?1", 0x6c000000, 0xff8080f0, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcmp", "?f,?0P", 0, (int) M_VFPU_C0_S, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcmp", "?f,?0", 0x6c000000, 0xffff80f0, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcmp", "?G", 0x6c000000, 0xfffffff0, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vmin", "?2p,?0P,?1P", 0, (int) M_VFPU_D_S_T, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vmin", "?2,?0,?1", 0x6d000000, 0xff808080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vmax", "?2p,?0P,?1P", 0, (int) M_VFPU_D_S_T, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vmax", "?2,?0,?1", 0x6d800000, 0xff808080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsgn", "?2p,?0P", 0, (int) M_VFPU_D_S, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsgn", "?2,?0", 0xd04a0000, 0xffff8080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcst", "?2p,?I", 0, (int) M_VCST, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcst", "?2,?I", 0xd0600000, 0xffe0ff80, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vscmp", "?2p,?0P,?1P", 0, (int) M_VFPU_D_S_T, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vscmp", "?2,?0,?1", 0x6e800000, 0xff808080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsge", "?2p,?0P,?1P", 0, (int) M_VFPU_D_S_T, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsge", "?2,?0,?1", 0x6f000000, 0xff808080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vslt", "?2p,?0P,?1P", 0, (int) M_VFPU_D_S_T, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vslt", "?2,?0,?1", 0x6f800000, 0xff808080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vi2uc", "?$p,?0", 0, (int) M_VFPU_D1_SP, INSN_MACRO, VF_Q, AL, 0, 0 },
{"vi2uc", "?$,?0", 0xd03c0000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vi2c", "?$p,?0", 0, (int) M_VFPU_D1_SP, INSN_MACRO, VF_Q, AL, 0, 0 },
{"vi2c", "?$,?0", 0xd03d0000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vi2us", "?(p,?0", 0, (int) M_VFPU_DP_SP, INSN_MACRO, VF_Q, AL, 0, 0 },
{"vi2us", "?(,?0", 0xd03e0000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vi2us", "?$p,?0", 0, (int) M_VFPU_D1_SP, INSN_MACRO, VF_P, AL, 0, 0 },
{"vi2us", "?$,?0", 0xd03e0000, 0xffff8080, RD_C2, VF_P, AL, 0, 0 },
{"vi2s", "?(p,?0", 0, (int) M_VFPU_D2_SP, INSN_MACRO, VF_Q, AL, 0, 0 },
{"vi2s", "?(,?0", 0xd03f0000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vi2s", "?$p,?0", 0, (int) M_VFPU_D1_SP, INSN_MACRO, VF_P, AL, 0, 0 },
{"vi2s", "?$,?0", 0xd03f0000, 0xffff8080, RD_C2, VF_P, AL, 0, 0 },
{"vmov", "?2p,?0P", 0, (int) M_VFPU_D_S, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vmov", "?2,?0", 0xd0000000, 0xffff8080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vabs", "?2p,?0", 0, (int) M_VFPU_D_SP, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vabs", "?2,?0", 0xd0010000, 0xffff8080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vneg", "?2p,?0", 0, (int) M_VFPU_D_SP, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vneg", "?2,?0", 0xd0020000, 0xffff8080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vidt", "?2p", 0, (int) M_VFPU_D, INSN_MACRO, VF_P|VF_Q, AL, 0, 0 },
{"vidt", "?2", 0xd0030000, 0xffffff80, RD_C2, VF_P|VF_Q, AL, 0, 0 },
{"vsat0", "?2,?0P", 0, (int) M_VFPU_DP_S, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsat0", "?2,?0", 0xd0040000, 0xffff8080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsat1", "?2,?0P", 0, (int) M_VFPU_DP_S, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsat1", "?2,?0", 0xd0050000, 0xffff8080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vzero", "?2p", 0, (int) M_VFPU_D, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vzero", "?2", 0xd0060000, 0xffffff80, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vone", "?2p", 0, (int) M_VFPU_D, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vone", "?2", 0xd0070000, 0xffffff80, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vrcp", "?2,?0", 0xd0100000, 0xffff8080, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vrsq", "?2,?0", 0xd0110000, 0xffff8080, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsin", "?2,?0", 0xd0120000, 0xffff8080, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcos", "?2,?0", 0xd0130000, 0xffff8080, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vexp2", "?2,?0", 0xd0140000, 0xffff8080, RD_C2, VFCF|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vlog2", "?2,?0", 0xd0150000, 0xffff8080, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vsqrt", "?2,?0", 0xd0160000, 0xffff8080, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vasin", "?2,?0", 0xd0170000, 0xffff8080, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vnrcp", "?2,?0", 0xd0180000, 0xffff0000, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vnsin", "?2,?0", 0xd01a0000, 0xffff8080, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vrexp2", "?2,?0", 0xd01c0000, 0xffff8080, RD_C2, VFCF|VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vrndi", "?2", 0xd0210000, 0xffffff80, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vrndf1", "?2", 0xd0220000, 0xffffff80, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vrndf2", "?2", 0xd0230000, 0xffffff80, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vf2h", "?(p,?0P", 0, (int) M_VFPU_D2_S, INSN_MACRO, VF_Q, AL, 0, 0 },
{"vf2h", "?(,?0", 0xd0320000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vf2h", "?$p,?0P", 0, (int) M_VFPU_D1_S, INSN_MACRO, VF_P, AL, 0, 0 },
{"vf2h", "?$,?0", 0xd0320000, 0xffff8080, RD_C2, VF_P, AL, 0, 0 },
{"vsrt1", "?2p,?0P", 0, (int) M_VFPU_D_S, INSN_MACRO, VF_Q, AL, 0, 0 },
{"vsrt1", "?2,?0", 0xd0400000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vsrt2", "?2p,?0P", 0, (int) M_VFPU_D_S, INSN_MACRO, VF_Q, AL, 0, 0 },
{"vsrt2", "?2,?0", 0xd0410000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vsrt3", "?2p,?0P", 0, (int) M_VFPU_D_S, INSN_MACRO, VF_Q, AL, 0, 0 },
{"vsrt3", "?2,?0", 0xd0480000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vsrt4", "?2p,?0P", 0, (int) M_VFPU_D_S, INSN_MACRO, VF_Q, AL, 0, 0 },
{"vsrt4", "?2,?0", 0xd0490000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vbfy1", "?2p,?0P", 0, (int) M_VFPU_D_S, INSN_MACRO, VF_P|VF_Q, AL, 0, 0 },
{"vbfy1", "?2,?0", 0xd0420000, 0xffff8080, RD_C2, VF_P|VF_Q, AL, 0, 0 },
{"vbfy2", "?2p,?0P", 0, (int) M_VFPU_D_S, INSN_MACRO, VF_Q, AL, 0, 0 },
{"vbfy2", "?2,?0", 0xd0430000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vocp", "?2p,?0", 0, (int) M_VFPU_D_SP, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vocp", "?2,?0", 0xd0440000, 0xffff8080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vfad", "?$P,?0p", 0, (int) M_VFPU_D1_S, INSN_MACRO, VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vfad", "?$,?0", 0xd0460000, 0xffff8080, RD_C2, VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vavg", "?$P,?0p", 0, (int) M_VFPU_D1_S, INSN_MACRO, VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vavg", "?$,?0", 0xd0470000, 0xffff8080, RD_C2, VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vf2in", "?2P,?0p,?S", 0, (int) M_VFPU_D_S_SC, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vf2in", "?2,?0,?S", 0xd2000000, 0xffe08080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vf2iz", "?2P,?0p,?S", 0, (int) M_VFPU_D_S_SC, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vf2iz", "?2,?0,?S", 0xd2200000, 0xffe08080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vf2iu", "?2P,?0p,?S", 0, (int) M_VFPU_D_S_SC, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vf2iu", "?2,?0,?S", 0xd2400000, 0xffe08080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vf2id", "?2P,?0p,?S", 0, (int) M_VFPU_D_S_SC, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vf2id", "?2,?0,?S", 0xd2600000, 0xffe08080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vi2f", "?2P,?0,?S", 0, (int) M_VFPU_D_SP_SC, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vi2f", "?2,?0,?S", 0xd2800000, 0xffe08080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcmov", "?2P,?0p,?M", 0, (int) M_VCMOV, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcmovt", "?2P,?0p,?M", 0, (int) M_VFPU_D_S_MC, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcmovt", "?2,?0,?M", 0xd2a00000, 0xfff88080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcmovf", "?2P,?0p,?M", 0, (int) M_VFPU_D_S_MC, INSN_MACRO, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vcmovf", "?2,?0,?M", 0xd2a80000, 0xfff88080, RD_C2, VF_S|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vmmul", "?>,?<,?=", 0xf0000000, 0xff808080, RD_C2, VFCFL|VF_P|VF_T|VF_Q, AL, 0, 0 },/* MATRIX */
{"vtfm4", "?/,?9,?.", 0xf1800000, 0xff808080, RD_C2, VFCFL|VF_Q, AL, 0, 0 },
{"vhtfm4", "?/,?9,?.", 0xf1800000, 0xff808080, RD_C2, VFCFL|VF_Q, AL, 0, 0 },
{"vmscl", "?>,?<,?#", 0xf2000000, 0xff808080, RD_C2, VFCF|VF_P|VF_T|VF_Q, AL, 0, 0 },/* MATRIX */
{"vqmul", "?2,?0,?1", 0xf2800000, 0xff808080, RD_C2, VFCFL|VF_Q, AL, 0, 0 },
{"vmmov", "?>,?<", 0xf3800000, 0xffff8080, RD_C2, VFCF|VF_P|VF_T|VF_Q, AL, 0, 0 },/* MATRIX */
{"vmidt", "?>", 0xf3830000, 0xffffff80, RD_C2, VF_P|VF_T|VF_Q, AL, 0, 0 },/* MATRIX */
{"vmzero", "?>", 0xf3860000, 0xffffff80, RD_C2, VF_P|VF_T|VF_Q, AL, 0, 0 },/* MATRIX */
{"vmone", "?>", 0xf3870000, 0xffffff80, RD_C2, VF_P|VF_T|VF_Q, AL, 0, 0 },/* MATRIX */
{"vrot", "?2,?!,?R", 0xf3a00000, 0xffe08080, RD_C2, VFCF|VF_P|VF_T|VF_Q, AL, 0, 0 },
{"vt4444", "?&,?0", 0xd0590000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vt5551", "?&,?0", 0xd05a0000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vt5650", "?&,?0", 0xd05b0000, 0xffff8080, RD_C2, VF_Q, AL, 0, 0 },
{"vcrs", "?2p,?0,?1", 0, (int) M_VFPU_D_SP_TP, INSN_MACRO, VF_T, AL, 0, 0 },
{"vcrs", "?2,?0,?1", 0x66800000, 0xff808080, RD_C2, VF_T, AL, 0, 0 },
{"vtfm3.t", "?(,?6,?&", 0xf1008000, 0xff808080, RD_C2, VFCFL, AL, 0, 0 },
{"vhtfm3.t", "?(,?6,?&", 0xf1000080, 0xff808080, RD_C2, VFCFL, AL, 0, 0 },
{"vcrsp", "?2,?0,?1", 0xf2800000, 0xff808080, RD_C2, VF_T, AL, 0, 0 },
{"vdet", "?$p,?0P,?1", 0, (int) M_VFPU_D1_S_TP, INSN_MACRO, VF_P, AL, 0, 0 },
{"vdet", "?$,?0,?1", 0x67000000, 0xff808080, RD_C2, VF_P, AL, 0, 0 },
{"vus2i", "?/p,?0", 0, (int) M_VFPU_D4_SP, INSN_MACRO, VF_P, AL, 0, 0 },
{"vus2i", "?/,?0", 0xd03a0000, 0xffff8080, RD_C2, VF_P, AL, 0, 0 },
{"vus2i", "?(p,?0", 0, (int) M_VFPU_D2_SP, INSN_MACRO, VF_S, AL, 0, 0 },
{"vus2i", "?(,?0", 0xd03a0000, 0xffff8080, RD_C2, VF_S, AL, 0, 0 },
{"vs2i", "?/p,?0", 0, (int) M_VFPU_D4_SP, RD_C2, VF_P, AL, 0, 0 },
{"vs2i", "?/,?0", 0xd03b0000, 0xffff8080, RD_C2, VF_P, AL, 0, 0 },
{"vs2i", "?(p,?0", 0, (int) M_VFPU_D2_SP, INSN_MACRO, VF_S, AL, 0, 0 },
{"vs2i", "?(,?0", 0xd03b0000, 0xffff8080, RD_C2, VF_S, AL, 0, 0 },
{"vh2f", "?/p,?0", 0, (int) M_VFPU_D4_SP, INSN_MACRO, VF_P, AL, 0, 0 },
{"vh2f", "?/,?0", 0xd0330000, 0xffff8080, RD_C2, VF_P, AL, 0, 0 },
{"vh2f", "?(p,?0", 0, (int) M_VFPU_D2_SP, INSN_MACRO, VF_S, AL, 0, 0 },
{"vh2f", "?(,?0", 0xd0330000, 0xffff8080, RD_C2, VF_S, AL, 0, 0 },
{"vsocp", "?/,?0", 0xd0450000, 0xffff8080, RD_C2, VF_P, AL, 0, 0 },
{"vsocp", "?(,?0", 0xd0450000, 0xffff8080, RD_C2, VF_S, AL, 0, 0 },
{"vtfm2", "?(,?3,?&", 0xf0800000, 0xff808080, RD_C2, VFCFL|VF_P, AL, 0, 0 },
{"vhtfm2", "?(,?3,?&", 0xf0800000, 0xff808080, RD_C2, VFCFL|VF_P, AL, 0, 0 },
{"vrnds", "?!", 0xd0200000, 0xffff80ff, RD_C2, VF_S, AL, 0, 0 },
{"vsbz", "?2,?0", 0xd0360000, 0xffff8080, RD_C2, VF_S, AL, 0, 0 },
{"vsbn", "?2,?0,?1", 0x61000000, 0xff808080, RD_C2, VF_S, AL, 0, 0 },
{"vlgb", "?2,?0", 0xd0370000, 0xffff8080, RD_C2, VF_S, AL, 0, 0 },
{"vwbn", "?2,?0,?W", 0xd3000000, 0xff008080, RD_C2, VF_S, AL, 0, 0 },
{"vpfxs", "?P", 0xdc000000, 0xff000000, RD_C2, 0, AL, 0, 0 },
{"vpfxt", "?P", 0xdd000000, 0xff000000, RD_C2, 0, AL, 0, 0 },
{"vpfxd", "?p", 0xde000000, 0xff000000, RD_C2, 0, AL, 0, 0 },
{"viim", "?1p,j", 0, (int) M_VIIM, INSN_MACRO, VF_S, AL, 0, 0 },
{"viim", "?1,j", 0xdf000000, 0xff800000, RD_C2, VF_S, AL, 0, 0 },
{"vfim", "?1p,?h", 0, (int) M_VFIM, INSN_MACRO, VF_S, AL, 0, 0 },
{"vfim", "?1,?h", 0xdf800000, 0xff800000, RD_C2, VF_S, AL, 0, 0 },
{"vnop", "", 0xffff0000, 0xffffffff, RD_C2, 0, AL, 0, 0 },
{"vflush", "", 0xffff040d, 0xffffffff, RD_C2, 0, AL, 0, 0 },
{"vsync", "", 0xffff0320, 0xffffffff, RD_C2, 0, AL, 0, 0 },
{"vsync", "i", 0xffff0000, 0xffff0000, RD_C2, 0, AL, 0, 0 },
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