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# don't use latest version of ak, it's broken
#   pip install autokeras==1.0.19 --no-deps

import os
import numpy as np
import clip
import torch
import autokeras as ak

from PIL import Image

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My current questions are specifically around some of the syntax in the systems verilog and vhdl, and just confirming some of my assumptions. As you know, I’ve downloaded a few open source projects, synthesized them on AWS, and run them on their F1 instances. I’ve read through their source code trying to gain a high level understanding of their project, and of SV and VHDL, along with things like overclocking, undervolting, temperature control, max power draw, different boards, etc.

General questions about FPGAs:

• Compatibility between different boards, same FPGA chip
  • porting designs from one board to another.
    • c program changes
    • verilog and resynth
  • Footprint compatibility

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###example response for an anal scene

{
  "url": "https://link.to-some-anal.com/video.mp4",
  "ref_id": "my-custom-ref"
}

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"Programs must be written for people to read, and only incidentally for machines to execute."
source: http://web.mit.edu/alexmv/6.037/sicp.pdf

# this part was really elegantly done, it's readable, easy to understand, commented, concise.  
# it was magical but wasn't too out there, just needs a unit test and all is good.  

# Get subboxes
sub_areas = self.responsearea_set.all()
sub_areas_draw = map(lambda a: a.drawables(), sub_areas)
# Flatten

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### Keybase proof

I hereby claim:

  * I am xiamike on github.
  * I am michaelxia (https://keybase.io/michaelxia) on keybase.
  * I have a public key whose fingerprint is EB9A 0171 A29F AAC2 2EA1  90DF 76E3 E933 B24B D916

To claim this, I am signing this object:

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import sys
import os
import random

if __name__ == '__main__':
  if len(sys.argv) != 3:
    print "USAGE: python bad_file.py <FILE_NAME> <FILE_SIZE_KB>"
    quit()
size = sys.argv[2]
name = sys.argv[1]