fpga-07-29-2018.md

My current questions are specifically around some of the syntax in the systems verilog and vhdl, and just confirming some of my assumptions. As you know, I’ve downloaded a few open source projects, synthesized them on AWS, and run them on their F1 instances. I’ve read through their source code trying to gain a high level understanding of their project, and of SV and VHDL, along with things like overclocking, undervolting, temperature control, max power draw, different boards, etc.

General questions about FPGAs:

• Compatibility between different boards, same FPGA chip

  • porting designs from one board to another.
    • c program changes
    • verilog and resynth
  • Footprint compatibility
  • Parts compatibility
    • this is probably not true between 2 boards of different manufacturers?
    • ex. VCU1525 from xilinx vs a 3rd party’s Board with a VU9P
  • Does this require modifying the verilog to match new IO?
  • FPGA slang:
    • the fabric, DRAM, BRAM, URAM, vccint
    • A design that “times close well” or “WNS”.
    • I’ve seen some guys raise vccint to 0.95 and “go way beyond WNS”, pushing it to 600-700 mhz
    • ex. design with 1,047,500 LUT's to pass timing at 730MHz. WNS=+0.001ns.

• Vivado

  • I dont have a copy yet, but need to understand the basics.

• Look over some source code with me.

  • this code isn’t a mining algorithm, it’s higher level like loops, writing data to registers, etc.
  • I just want to make sure I’m understanding the syntax correctly.
  • writing to output
  • reading from input
  • importing submodules
  • c endianess vs fpga endianess

Next time if we are out of time.

• Drivers:
  • a friend was compiling windows drivers XDMA Windows Drivers
  • full or partial bitstream configuration over pice?
  • MCAP interface
• drivers are different for each board / manufacturer I assume?

• load keccak into vivado.

  • go over a keccak simulation with ketan.

    • input, outputs

  • go over synthesis, clock speed, etc

  • view different reports that are helpful?

    • view the layout of the logic?
    • view timings?

  • targeting the VCU1525

  • c code - conceptually how would we talk to the FPGA.

    • fd that points to the PCI slot.
    • mmap gets us a buffer to write to the FPGA
      • addressing registers?
      • sizing?
    • swapping endianness before writing to FPGA?

  • now doing the above targeting different Board

    • Do we need to change verilog?
    • Do we need to change C and mmap?

• Do we need drivers for different FPGA boards?

• Or not since it’s over serial PCI?

• partial reconfiguration of Xilinx VU9P?

• Programming fpga’s over PCI

• what are these when simulating?

  • ports
  • constraints.