My current questions are specifically around some of the syntax in the systems verilog and vhdl, and just confirming some of my assumptions. As you know, I’ve downloaded a few open source projects, synthesized them on AWS, and run them on their F1 instances. I’ve read through their source code trying to gain a high level understanding of their project, and of SV and VHDL, along with things like overclocking, undervolting, temperature control, max power draw, different boards, etc.
General questions about FPGAs:
- Compatibility between different boards, same FPGA chip
- porting designs from one board to another.
- c program changes
- verilog and resynth
- Footprint compatibility
- porting designs from one board to another.