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November 17, 2013 22:37
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-- Company: | |
-- Engineer: | |
-- | |
-- Create Date: 03:08:10 11/16/2013 | |
-- Design Name: | |
-- Module Name: stoperica - Behavioral | |
-- Project Name: | |
-- Target Devices: | |
-- Tool versions: | |
-- Description: | |
-- | |
-- Dependencies: | |
-- | |
-- Revision: | |
-- Revision 0.01 - File Created | |
-- Additional Comments: | |
-- | |
---------------------------------------------------------------------------------- | |
library IEEE; | |
use IEEE.STD_LOGIC_1164.ALL; | |
-- Uncomment the following library declaration if using | |
-- arithmetic functions with Signed or Unsigned values | |
--use IEEE.NUMERIC_STD.ALL; | |
use IEEE.STD_LOGIC_UNSIGNED.ALL; | |
-- Uncomment the following library declaration if instantiating | |
-- any Xilinx primitives in this code. | |
--library UNISIM; | |
--use UNISIM.VComponents.all; | |
entity stoperica is | |
Port ( iCLK : in STD_LOGIC; | |
iRST : in STD_LOGIC; | |
iSTOP : in STD_LOGIC; | |
iSTART : in STD_LOGIC; | |
iCOUNTINUE : in STD_LOGIC; | |
oSEC : out STD_LOGIC_VECTOR (7 downto 0)); | |
end stoperica; | |
architecture Behavioral of stoperica is | |
signal sDIVOUT : STD_LOGIC; | |
signal sDIVCNT : STD_LOGIC_VECTOR (7 downto 0); | |
signal sSECCNT : STD_LOGIC_VECTOR (7 downto 0); | |
signal sENABLE : STD_LOGIC; | |
begin | |
process (iCLK) begin | |
if (iCLK'event and iCLK = '1') then | |
if( iRST = '0') then | |
sDIVCNT <= (others => '0'); | |
sDIVOUT <= '0'; | |
sSECCNT <= (others => '0'); | |
sENABLE <= '0'; | |
elsif (iSTART = '1') then | |
if(sENABLE = '1') then | |
sDIVCNT <= (others => '0'); | |
sDIVOUT <= '0'; | |
sSECCNT <= (others => '0'); | |
else | |
sENABLE <= '1'; | |
end if; | |
elsif (iSTOP = '1') then | |
sENABLE <= '0'; | |
elsif ( iCOUNTINUE = '1' and sENABLE = '0') then | |
sENABLE <= '1'; | |
else | |
if (sENABLE = '1') then | |
if (sDIVCNT = "00010111") then | |
sDIVCNT <= (others => '0'); | |
sDIVOUT <= '0'; | |
sSECCNT <= sSECCNT + 1; | |
else | |
sDIVCNT <= sDIVCNT+1; | |
end if; | |
else | |
sSECCNT <= sSECCNT; | |
end if; | |
end if; | |
end if; | |
end process; | |
oSEC <= sSECCNT; | |
end Behavioral; |
Can u explain me those signals what they mean ?
thank you !
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