A PWM module for JPU16

JPU16_PWM.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;



entity JPU16_PWM is
	Generic( BusAncho: integer := 16);
	Port(
			SysClk:  in	STD_LOGIC;
			IO_Addr: in STD_LOGIC_VECTOR( BusAncho-1 downto 0);
			IO_Dout: in STD_LOGIC_VECTOR( BusAncho-1 downto 0);
			IO_Din:  out STD_LOGIC_VECTOR( BusAncho-1 downto 0);
			IO_RD: 	in STD_LOGIC;
			IO_WE: 	in STD_LOGIC;
			Reset:   in STD_LOGIC;
			
			PwmOut:  out STD_LOGIC
		
	);
end JPU16_PWM;

architecture Behavioral of JPU16_PWM is
	
	signal ControlPwmReg: std_logic_vector (BusAncho/2 -1 downto 0) := (others => '0');
	
	alias Pwm_Enable: std_logic is ControlPwmReg(0);
	alias PhaseBit: 	std_logic is ControlPwmReg(2);
	
	signal PrescalerCount: std_logic_vector (BusAncho-1 downto 0) := (others => '0');
	signal PrescalerReg:   std_logic_vector (BusAncho-1 downto 0) := (others => '0');
	
	signal CountEnable:  std_logic;
	
	signal CountPwm: 		std_logic_vector (BusAncho-1 downto 0) := (others => '0');
	signal DutyCyclePwm: std_logic_vector (BusAncho-1 downto 0) := (others => '0');
	
	signal PwmOutReg:    std_logic;
	
	alias	 PolOut: 		std_logic is ControlPwmReg(1);
	
	signal PhaseControlBit: std_logic := '0';
	
begin

	CountEnable <= '1' when PrescalerReg = PrescalerCount else '0';
	
	
	process(SysClk, Pwm_Enable)
	begin
		if rising_edge(SysClk) then
			if Pwm_Enable = '1' then
				PrescalerCount <= PrescalerCount + 1;				
			else
				PrescalerCount <= (others => '0');
			end if;
		end if;
	end process;
	
-----------------------------------------------------------	
	process(SysClk, Pwm_Enable, CountEnable, PhaseControlBit)
	begin
		if rising_edge(SysClk) then
			if Pwm_Enable = '1' then
				if  CountEnable = '1' then
					if PhaseControlBit ='0' then
						CountPwm <= CountPwm + 1;			
					else
						CountPwm <= CountPwm - 1;			
					end if;
				end if;
			else
				CountPwm <= (others => '0');
			end if;
		end if;
	end process;
	

	PwmOutReg <= '1' when DutyCyclePwm < CountPwm else '0';
	PwmOut <= PwmOutReg xor PolOut;
	
	
	process(SysClk, PhaseBit, CountPwm)
	begin
		if rising_edge(SysClk) then
			if CountPwm = 0 or PhaseBit = '0' then
				PhaseControlBit <= '0';
			elsif CountPwm = (CountPwm'range => '1')then
				PhaseControlBit <= '1';
			end if;
		end if;
	end process;
	
end Behavioral;