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library IEEE; | |
use IEEE.STD_LOGIC_1164.ALL; | |
use IEEE.STD_LOGIC_UNSIGNED.ALL; | |
use IEEE.STD_LOGIC_ARITH.ALL; | |
entity DSM is | |
Port ( Clk : in STD_LOGIC; | |
SignalOut : out STD_LOGIC; | |
SignalIn : in STD_LOGIC_VECTOR (9 downto 0)); |
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ADCSET equ 0x0200 | |
RESULT equ 0x0100 | |
PORTBI equ 0x0010 | |
PORTB equ 0x0020 | |
DDRB equ 0x0030 | |
Periodo equ 0x0004 | |
CPReg equ 0x0008 | |
DCreg equ 0x000C |
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library IEEE; | |
use IEEE.STD_LOGIC_1164.ALL; | |
use IEEE.STD_LOGIC_UNSIGNED.ALL; | |
use IEEE.STD_LOGIC_ARITH.ALL; | |
entity JPU16_PWM is | |
Generic( BusAncho: integer := 16); | |
Port( |
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; Probano unidad de multiplicacion de JPU16 | |
; Autor: Jonathan Castro | |
; JPU16ASM | |
; | |
; | |
TMRCTRL equ 0xA000 | |
TMRPR equ 0x6000 | |
TMRCNT equ 0x2000 | |
DDRA equ 0x0001 | |
PORTA equ 0x0002 |
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library IEEE; | |
use IEEE.STD_LOGIC_1164.ALL; | |
use IEEE.STD_LOGIC_UNSIGNED.ALL; | |
use IEEE.STD_LOGIC_ARITH.ALL; | |
use work.JPU16_Pack.all; | |
entity SistemaPrincipal is | |
Generic( AnchoBus: integer := 16); | |
Port ( clk : in STD_LOGIC; | |
SalPort: out STD_LOGIC_VECTOR(AnchoBus-1 downto 0)); |
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-------------------------------------------------------------------------------- | |
-- Company: | |
-- Engineer: | |
-- | |
-- Create Date: 00:30:43 03/23/2012 | |
-- Design Name: | |
-- Module Name: /home/neo/Projects/FPGA/CPUNV/TB.vhd | |
-- Project Name: CPUNV | |
-- Target Device: | |
-- Tool versions: |
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library IEEE; | |
use IEEE.STD_LOGIC_1164.ALL; | |
use IEEE.STD_LOGIC_ARITH.ALL; | |
use IEEE.STD_LOGIC_UNSIGNED.ALL; | |
entity STimer is | |
generic( BusAncho: integer := 16; | |
Mascara: STD_LOGIC_VECTOR(15 downto 0) := X"E000"; | |
DirTMRCNT: STD_LOGIC_VECTOR(15 downto 0) := X"2000"; | |
DirTMRPR: STD_LOGIC_VECTOR(15 downto 0) := X"6000"; |