Delta Sigma

DSM.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity DSM is
    Port ( Clk : in  STD_LOGIC;
           SignalOut : out  STD_LOGIC;
           SignalIn : in  STD_LOGIC_VECTOR (9 downto 0));
end DSM;

architecture Behavioral of DSM is
	signal	feedback: STD_LOGIC_VECTOR( SignalIn'range ) := (others =>'0');
	signal	error: STD_LOGIC_VECTOR( SignalIn'range ) := (others =>'0');
	signal	integrator: STD_LOGIC_VECTOR(SignalIn'range) := (others => '0');
	signal	SignalOut_Q: std_logic := '0';
begin

	error <= SignalIn - feedback when rising_edge(Clk) else error;
	integrator <= integrator + error when rising_edge(Clk) else integrator;
	SignalOut_Q <= '1' when integrator(9) = '1' else '0';
	SignalOut <= SignalOut_Q;
	
	process (Clk, SignalOut_Q)
	begin
		if SignalOut_Q = '0'  then
			feedback <= "0000000000";
		else
			feedback <= "1111111111";
		end if;
	end process;
	


end Behavioral;