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deck_6502-instruction-names.txt

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<b>ADC</b> | <b>AD</b>d with <b>C</b>arry
<b>AND</b> (&lt;?&gt;) | <b>AND</b> (with accumulator)
<b>ASL</b> | <b>A</b>rithmetic <b>S</b>hift <b>L</b>eft
<b>BCC</b> | <b>B</b>ranch on <b>C</b>arry <b>C</b>lear
<b>BCS</b> | <b>B</b>ranch on <b>C</b>arry <b>S</b>et
<b>BEQ</b> (&lt;?&gt;) | <b>B</b>ranch on <b>EQ</b>ual (zero set)
<b>BIT</b> | <b>BIT</b> <b>T</b>est
<b>BMI</b> (&lt;?&gt;) | <b>B</b>ranch on <b>MI</b>nus (negative set)
<b>BPL</b> (&lt;?&gt;) | <b>B</b>ranch on <b>PL</b>us (negative clear)
<b>BRK</b> / &lt;?&gt; | <b>BR</b>ea<b>K</b> / interrupt
<b>BVC</b> | <b>B</b>ranch on o<b>V</b>erflow <b>C</b>lear
<b>BVS</b> | <b>B</b>ranch on o<b>V</b>erflow <b>S</b>et
<b>CLC</b> | <b>CL</b>ear <b>C</b>arry
<b>CLD</b> | <b>CL</b>ear <b>D</b>ecimal
<b>CLI</b> &lt;?&gt; | <b>CL</b>ear <b>I</b>nterrupt disable
<b>CLV</b> | <b>CL</b>ear o<b>V</b>erflow
<b>CMP</b> (&lt;?&gt;) | <b>C</b>o<b>MP</b>are (with accumulator)
<b>CPX</b> | <b>C</b>om<b>P</b>are with <b>X</b>
<b>CPY</b> | <b>C</b>om<b>P</b>are with <b>Y</b>
<b>DEC</b> | <b>DEC</b>rement
<b>DEX</b> | <b>DE</b>crement X
<b>DEY</b> | <b>DE</b>crement <b>Y</b>
<b>EOR</b> (&lt;?&gt;) | <b>E</b>xclusive <b>OR</b> (with accumulator)
<b>INC</b> | <b>INC</b>rement
<b>INX</b> | <b>IN</b>crement <b>X</b>
<b>INY</b> | <b>IN</b>crement <b>Y</b>
<b>JMP</b> | <b>J</b>u<b>MP</b>
<b>JSR</b> | <b>J</b>ump <b>S</b>ub<b>R</b>outine
<b>LDA</b> | <b>L</b>oa<b>D</b> <b>A</b>ccumulator
<b>LDX</b> | <b>L</b>oa<b>D</b> <b>X</b>
<b>LDY</b> | <b>L</b>oa<b>D</b> <b>Y</b>
<b>LSR</b> | <b>L</b>ogical <b>S</b>hift <b>R</b>ight
<b>NOP</b> | <b>NO</b> <b>OP</b>eration
<b>ORA</b> | <b>OR</b> with <b>A</b>ccumulator
<b>PHA</b> | <b>P</b>us<b>H</b> <b>A</b>ccumulator
<b>PHP</b> &lt;?&gt; | <b>P</b>us<b>H</b> <b>P</b>rocessor status
<b>PLA</b> | <b>P</b>u<b>LL</b> <b>A</b>ccumulator
<b>PLP</b> &lt;?&gt; | <b>P</b>u<b>LL P</b>rocessor status
<b>ROL</b> | <b>RO</b>tate <b>L</b>eft
<b>ROR</b> | <b>RO</b>tate <b>R</b>ight
<b>RTI</b> | <b>R</b>e<b>T</b>urn from <b>I</b>nterrupt
<b>RTS</b> | <b>R</b>e<b>T</b>urn from <b>S</b>ubroutine
<b>SBC</b> | <b>S</b>u<b>B</b>tract with <b>C</b>arry
<b>SEC</b> | <b>SE</b>t <b>C</b>arry
<b>SED</b> | <b>SE</b>t <b>D</b>ecimal
<b>SEI</b> &lt;?&gt; | <b>SE</b>t <b>I</b>nterrupt disable
<b>STA</b> | <b>ST</b>ore <b>A</b>ccumulator
<b>STX</b> | <b>ST</b>ore <b>X</b>
<b>STY</b> | <b>ST</b>ore <b>Y</b>
<b>TAX</b> | <b>T</b>ransfer <b>A</b>ccumulator to <b>X</b>
<b>TAY</b> | <b>T</b>ransfer <b>A</b>ccumulator to <b>Y</b>
<b>TSX</b> | <b>T</b>ransfer <b>S</b>tack pointer to <b>X</b>
<b>TXA</b> | <b>T</b>ransfer <b>X</b> to <b>A</b>ccumulator
<b>TXS</b> | <b>T</b>ransfer <b>X</b> to <b>S</b>tack pointer
<b>TYA</b> | <b>T</b>ransfer <b>Y</b> to <b>A</b>ccumulator
Register: <b>PC</b> (&lt;?&gt; bit) | <b>P</b>rogram <b>C</b>ounter (16 bit)
Register: <b>A</b> (&lt;?&gt; bit) | <b>A</b>ccumulator (8 bit)
Register: <b>X</b> (&lt;?&gt; bit) | <b>X</b> register (8 bit)
Register: <b>Y</b> (&lt;?&gt; bit) | Y register (8 bit)
Register: <b>P</b> (&lt;?&gt; bit) | <b>P</b>rocessor status register (8 bit)
Register: <b>S</b> (&lt;?&gt; bit) | <b>S</b>tack pointer (8 bit)
Processor state flag: <b>N</b> (bit &lt;?&gt;) | <b>N</b>egative (bit 7)
Processor state flag: <b>V</b> (bit &lt;?&gt;) | o<b>V</b>erflow (bit 6)
Processor state flag: <b>B</b> (bit &lt;?&gt;) | <b>B</b>reak (bit 4)
Processor state flag: <b>D</b> (bit &lt;?&gt;) | <b>D</b>ecimal (bit 3)
Processor state flag: <b>I</b> [&lt;?&gt;] (bit &lt;?&gt;) | <b>I</b>nterrupt [IRQ disable] (bit 2)
Processor state flag: <b>Z</b> (bit &lt;?&gt;) | <b>Z</b>ero (bit 1)
Processor state flag: <b>C</b> (bit &lt;?&gt;) | <b>C</b>arry (bit 0)