Zmigavac3.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;


entity zmigavac2 is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           inLEFT : in  STD_LOGIC;
           inRIGHT : in  STD_LOGIC;
           inHAZ : in  STD_LOGIC;
           oLEFT : out  STD_LOGIC_VECTOR (2 downto 0);
           oRIGHT : out  STD_LOGIC_VECTOR (2 downto 0));
end zmigavac2;

architecture Behavioral of zmigavac2 is
	type tSTATE is (IDLE,L1,L2,L3,R1,R2,R3,LR3);
	signal sSTATE : tSTATE;
	signal sLEFT : STD_LOGIC_VECTOR(2 downto 0);
	signal sRIGHT : STD_LOGIC_VECTOR(2 downto 0 );
	signal sTC : STD_LOGIC;
	signal sCNT : integer range 0 to 11;
begin	

process(iCLK,inRST) begin
		if(inRST='0') then
			sSTATE<=IDLE;
		elsif(iCLK'event and iCLK='1') then
			if(sTC='1') then
				case(sSTATE) is 
					when IDLE => 
						if(inLEFT='0' and inRIGHT='1' and inHAZ='1') then
							sSTATE<=L1;
						elsif(inRIGHT='0' and iNLEFT='0' and inHAZ='0') then
							sSTATE<=LR3;
						elsif(inRIGHT='0' and inLEFT='1' and inHAZ='1') then
							sSTATE<=R1;
						elsif(inRIGHT='0' and inLEFT='0' and inHAZ='1') then
							sSTATE<=LR3;
						elsif(inRIGHT='0' and inHAZ='0' and inLEFT='1') then
							sSTATE<=LR3;
						elsif(inLEFT='0' and inHAZ='0' and inRIGHT='1') then
							sSTATE<=LR3;
						elsif(inHAZ='0') then
							sSTATE<=LR3;
						end if;
					when L1 => if(inHAZ='0') then sSTATE<=LR3; else sSTATE<=L2; end if;
					when L2 => if(inHAZ='0') then sSTATE<=LR3; else sSTATE<=L3; end if;
					when L3 => if(inHAZ='0') then sSTATE<=LR3; else sSTATE<=IDLE; end if;
					when R1 => if(inHAZ='0') then sSTATE<=LR3; else sSTATE<=R2; end if;
					when R2 => if(inHAZ='0') then sSTATE<=LR3; else sSTATE<=R3; end if;
					when R3 => if(inHAZ='0') then sSTATE<=LR3; else sSTATE<=IDLE; end if;
					when LR3 => sSTATE<=IDLE;
			end case;
			end if;
			end if;
		end process;
		
process(sSTATE) begin
	case sSTATE is
		
		when IDLE => sLEFT<="000"; sRIGHT<="000";
		when L1 => sLEFT<="001"; sRIGHT<="000";
		when L2 => sLEFT<="011"; sRIGHT<="000";
		when L3 => sLEFT<="111"; sRIGHT<="000";
		when R1 => sLEFT<="000"; sRIGHT<="100";
		when R2 => sLEFT<="000"; sRIGHT<="110";
		when R3 => sLEFT<="000"; sRIGHT<="111";
		when LR3=> sLEFT<="111"; sRIGHT<="111";
	end case;
end process;

process(iCLK,inRST) begin
	if(inRST='0') then
		sCNT<=0;
	elsif(iCLK'event and iCLK='1') then
		if(sCNT=11) then
			sCNT<=0;
		else
			sCNT<=sCNT+1;
		end if;
	end if;
end process;	
sTC<='1' when sCNT=11 else '0';
oRIGHT<=sRIGHT;
oLEFT<=sLEFT;
	
end Behavioral;