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Vivado SystemVerilog Makefile
XVLOG_FILES=xvlog.log xvlog.pb xsim.dir/
XELAB_FILES=webtalk*.log webtalk*.jou xelab.log xelab.pb .Xil/
XSIM_FILES=xsim*.log xsim*.jou work.top.wdb
all: xsim.dir/
xsim.dir/: *.sv
@echo "Parsing HDL"
@xvlog --sv *.sv
@echo "Elaborating design"
@xelab top -debug all
test: xsim.dir/
@echo "Starting simulation"
@xsim -R top
test-gui: xsim.dir/
@echo "Starting simulation"
@xsim -g top
clean:
rm -rf $(XVLOG_FILES) $(XELAB_FILES) $(XSIM_FILES)
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