Skip to content

Instantly share code, notes, and snippets.

Show Gist options
  • Save MrVan/720b023e5b5e4bd92043af31c1cb3bcf to your computer and use it in GitHub Desktop.
Save MrVan/720b023e5b5e4bd92043af31c1cb3bcf to your computer and use it in GitHub Desktop.
port of u-boot CAAM code to OP-TEE
From f6e25ec9d9a5cbf6b482cc7d8306b6dc9e42ac8f Mon Sep 17 00:00:00 2001
From: Jangseop Shin <jsshin@sor.snu.ac.kr>
Date: Wed, 22 Feb 2017 18:20:08 +0900
Subject: [PATCH 1/5] initial port of u-boot caam code
---
core/arch/arm/plat-imx/caam_cmds.c | 37 ++
core/arch/arm/plat-imx/caam_cmds.h | 8 +
core/arch/arm/plat-imx/clock.c | 32 ++
core/arch/arm/plat-imx/clock.h | 72 +++
core/arch/arm/plat-imx/conf.mk | 5 +
core/arch/arm/plat-imx/crm_regs.h | 1098 ++++++++++++++++++++++++++++++++++++
core/arch/arm/plat-imx/imx-regs.h | 917 ++++++++++++++++++++++++++++++
core/arch/arm/plat-imx/sub.mk | 1 +
core/drivers/crypto/desc.h | 666 ++++++++++++++++++++++
core/drivers/crypto/desc_constr.h | 284 ++++++++++
core/drivers/crypto/error.c | 261 +++++++++
core/drivers/crypto/fsl_blob.c | 110 ++++
core/drivers/crypto/jobdesc.c | 274 +++++++++
core/drivers/crypto/jobdesc.h | 40 ++
core/drivers/crypto/jr.c | 489 ++++++++++++++++
core/drivers/crypto/jr.h | 99 ++++
core/drivers/crypto/misc.h | 16 +
core/drivers/crypto/sub.mk | 1 +
core/drivers/sub.mk | 2 +
core/include/fsl_sec.h | 267 +++++++++
20 files changed, 4679 insertions(+)
create mode 100644 core/arch/arm/plat-imx/caam_cmds.c
create mode 100644 core/arch/arm/plat-imx/caam_cmds.h
create mode 100644 core/arch/arm/plat-imx/clock.c
create mode 100644 core/arch/arm/plat-imx/clock.h
create mode 100644 core/arch/arm/plat-imx/crm_regs.h
create mode 100644 core/arch/arm/plat-imx/imx-regs.h
create mode 100644 core/drivers/crypto/desc.h
create mode 100644 core/drivers/crypto/desc_constr.h
create mode 100644 core/drivers/crypto/error.c
create mode 100644 core/drivers/crypto/fsl_blob.c
create mode 100644 core/drivers/crypto/jobdesc.c
create mode 100644 core/drivers/crypto/jobdesc.h
create mode 100644 core/drivers/crypto/jr.c
create mode 100644 core/drivers/crypto/jr.h
create mode 100644 core/drivers/crypto/misc.h
create mode 100644 core/drivers/crypto/sub.mk
create mode 100644 core/include/fsl_sec.h
diff --git a/core/arch/arm/plat-imx/caam_cmds.c b/core/arch/arm/plat-imx/caam_cmds.c
new file mode 100644
index 0000000..40332d0
--- /dev/null
+++ b/core/arch/arm/plat-imx/caam_cmds.c
@@ -0,0 +1,37 @@
+#include <caam_cmds.h>
+#include <clock.h>
+#include <imx-regs.h>
+#include <io.h>
+#include <stdint.h>
+#include <trace.h>
+#include "fsl_sec.h"
+
+/**
+* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
+* @src: - Address of data to be encapsulated
+* @dst: - Desination address of encapsulated data
+* @len: - Size of data to be encapsulated
+*
+* Returns zero on success,and negative on error.
+*/
+/*static*/ int blob_encap_dek(const uint8_t *src, uint8_t *dst, uint32_t len)
+{
+ int ret = 0;
+ uint32_t jr_size = 4;
+
+ uint32_t out_jr_size = read32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
+ if (out_jr_size != jr_size) {
+ caam_clock_enable(1);
+ sec_init();
+ }
+
+ if (!((len == 128) | (len == 192) | (len == 256))) {
+ EMSG("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
+ return -1;
+ }
+
+ len /= 8;
+ ret = blob_dek(src, dst, len);
+
+ return ret;
+}
diff --git a/core/arch/arm/plat-imx/caam_cmds.h b/core/arch/arm/plat-imx/caam_cmds.h
new file mode 100644
index 0000000..4f3bbd9
--- /dev/null
+++ b/core/arch/arm/plat-imx/caam_cmds.h
@@ -0,0 +1,8 @@
+#ifndef CAAM_CMDS_H
+#define CAAM_CMDS_H
+
+#include <stdint.h>
+
+int blob_encap_dek(const uint8_t *src, uint8_t *dst, uint32_t len);
+
+#endif /* CAAM_CMDS_H */
diff --git a/core/arch/arm/plat-imx/clock.c b/core/arch/arm/plat-imx/clock.c
new file mode 100644
index 0000000..64bc93b
--- /dev/null
+++ b/core/arch/arm/plat-imx/clock.c
@@ -0,0 +1,32 @@
+#include <io.h>
+#include <clock.h>
+#include <crm_regs.h>
+#include <imx-regs.h>
+#include "fsl_sec.h"
+
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+void caam_clock_enable(unsigned char enable)
+{
+ uint32_t reg;
+
+ /* CG4 ~ CG6, CAAM clocks */
+ reg = read32((vaddr_t)&imx_ccm->CCGR0);
+ if (enable)
+ reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ else
+ reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ write32(reg, (vaddr_t)&imx_ccm->CCGR0);
+
+ /* EMI slow clk */
+ reg = read32((vaddr_t)&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ write32(reg, (vaddr_t)&imx_ccm->CCGR6);
+}
diff --git a/core/arch/arm/plat-imx/clock.h b/core/arch/arm/plat-imx/clock.h
new file mode 100644
index 0000000..29084a6
--- /dev/null
+++ b/core/arch/arm/plat-imx/clock.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef CLOCK_H
+#define CLOCK_H
+
+#include <stdint.h>
+
+#ifdef CONFIG_SYS_MX6_HCLK
+#define MXC_HCLK CONFIG_SYS_MX6_HCLK
+#else
+#define MXC_HCLK 24000000
+#endif
+
+#ifdef CONFIG_SYS_MX6_CLK32
+#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
+#else
+#define MXC_CLK32 32768
+#endif
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_PER_CLK,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_IPG_PERCLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_AXI_CLK,
+ MXC_EMI_SLOW_CLK,
+ MXC_DDR_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_ESDHC4_CLK,
+ MXC_SATA_CLK,
+ MXC_NFC_CLK,
+ MXC_I2C_CLK,
+};
+
+enum enet_freq {
+ ENET_25MHZ,
+ ENET_50MHZ,
+ ENET_100MHZ,
+ ENET_125MHZ,
+};
+
+uint32_t imx_get_uartclk(void);
+uint32_t imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+void setup_gpmi_io_clk(uint32_t cfg);
+void caam_clock_enable(unsigned char enable);
+void enable_ocotp_clk(unsigned char enable);
+void enable_usboh3_clk(unsigned char enable);
+void enable_uart_clk(unsigned char enable);
+int enable_cspi_clock(unsigned char enable, unsigned spi_num);
+int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
+int enable_sata_clock(void);
+void disable_sata_clock(void);
+int enable_pcie_clock(void);
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+int enable_spi_clk(unsigned char enable, unsigned spi_num);
+void enable_ipu_clock(void);
+int enable_fec_anatop_clock(enum enet_freq freq);
+void enable_enet_clk(unsigned char enable);
+void enable_qspi_clk(int qspi_num);
+void enable_thermal_clk(void);
+#endif /* CLOCK_H */
diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk
index 785736a..3cdbc9c 100644
--- a/core/arch/arm/plat-imx/conf.mk
+++ b/core/arch/arm/plat-imx/conf.mk
@@ -26,6 +26,11 @@ $(call force,CFG_SECURE_TIME_SOURCE_REE,y)
CFG_BOOT_SYNC_CPU ?= y
CFG_BOOT_SECONDARY_REQUEST ?= y
+
+$(call force,CFG_MX6,y)
+CFG_FSL_CAAM ?= y
+CFG_SYS_FSL_SEC_COMPAT ?= 4
+CFG_SYS_FSL_SEC_LE ?= y
endif
ta-targets = ta_arm32
diff --git a/core/arch/arm/plat-imx/crm_regs.h b/core/arch/arm/plat-imx/crm_regs.h
new file mode 100644
index 0000000..c96afb7
--- /dev/null
+++ b/core/arch/arm/plat-imx/crm_regs.h
@@ -0,0 +1,1098 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef CCM_REGS_H
+#define CCM_REGS_H
+
+#define CCM_CCOSR 0x020c4060
+#define CCM_CCGR0 0x020C4068
+#define CCM_CCGR1 0x020C406c
+#define CCM_CCGR2 0x020C4070
+#define CCM_CCGR3 0x020C4074
+#define CCM_CCGR4 0x020C4078
+#define CCM_CCGR5 0x020C407c
+#define CCM_CCGR6 0x020C4080
+
+#define PMU_MISC2 0x020C8170
+
+#ifndef __ASSEMBLY__
+struct mxc_ccm_reg {
+ uint32_t ccr; /* 0x0000 */
+ uint32_t ccdr;
+ uint32_t csr;
+ uint32_t ccsr;
+ uint32_t cacrr; /* 0x0010*/
+ uint32_t cbcdr;
+ uint32_t cbcmr;
+ uint32_t cscmr1;
+ uint32_t cscmr2; /* 0x0020 */
+ uint32_t cscdr1;
+ uint32_t cs1cdr;
+ uint32_t cs2cdr;
+ uint32_t cdcdr; /* 0x0030 */
+ uint32_t chsccdr;
+ uint32_t cscdr2;
+ uint32_t cscdr3;
+ uint32_t cscdr4; /* 0x0040 */
+ uint32_t resv0;
+ uint32_t cdhipr;
+ uint32_t cdcr;
+ uint32_t ctor; /* 0x0050 */
+ uint32_t clpcr;
+ uint32_t cisr;
+ uint32_t cimr;
+ uint32_t ccosr; /* 0x0060 */
+ uint32_t cgpr;
+ uint32_t CCGR0;
+ uint32_t CCGR1;
+ uint32_t CCGR2; /* 0x0070 */
+ uint32_t CCGR3;
+ uint32_t CCGR4;
+ uint32_t CCGR5;
+ uint32_t CCGR6; /* 0x0080 */
+ uint32_t CCGR7;
+ uint32_t cmeor;
+ uint32_t resv[0xfdd];
+ uint32_t analog_pll_sys; /* 0x4000 */
+ uint32_t analog_pll_sys_set;
+ uint32_t analog_pll_sys_clr;
+ uint32_t analog_pll_sys_tog;
+ uint32_t analog_usb1_pll_480_ctrl; /* 0x4010 */
+ uint32_t analog_usb1_pll_480_ctrl_set;
+ uint32_t analog_usb1_pll_480_ctrl_clr;
+ uint32_t analog_usb1_pll_480_ctrl_tog;
+ uint32_t analog_reserved0[4];
+ uint32_t analog_pll_528; /* 0x4030 */
+ uint32_t analog_pll_528_set;
+ uint32_t analog_pll_528_clr;
+ uint32_t analog_pll_528_tog;
+ uint32_t analog_pll_528_ss; /* 0x4040 */
+ uint32_t analog_reserved1[3];
+ uint32_t analog_pll_528_num; /* 0x4050 */
+ uint32_t analog_reserved2[3];
+ uint32_t analog_pll_528_denom; /* 0x4060 */
+ uint32_t analog_reserved3[3];
+ uint32_t analog_pll_audio; /* 0x4070 */
+ uint32_t analog_pll_audio_set;
+ uint32_t analog_pll_audio_clr;
+ uint32_t analog_pll_audio_tog;
+ uint32_t analog_pll_audio_num; /* 0x4080*/
+ uint32_t analog_reserved4[3];
+ uint32_t analog_pll_audio_denom; /* 0x4090 */
+ uint32_t analog_reserved5[3];
+ uint32_t analog_pll_video; /* 0x40a0 */
+ uint32_t analog_pll_video_set;
+ uint32_t analog_pll_video_clr;
+ uint32_t analog_pll_video_tog;
+ uint32_t analog_pll_video_num; /* 0x40b0 */
+ uint32_t analog_reserved6[3];
+ uint32_t analog_pll_video_denom; /* 0x40c0 */
+ uint32_t analog_reserved7[7];
+ uint32_t analog_pll_enet; /* 0x40e0 */
+ uint32_t analog_pll_enet_set;
+ uint32_t analog_pll_enet_clr;
+ uint32_t analog_pll_enet_tog;
+ uint32_t analog_pfd_480; /* 0x40f0 */
+ uint32_t analog_pfd_480_set;
+ uint32_t analog_pfd_480_clr;
+ uint32_t analog_pfd_480_tog;
+ uint32_t analog_pfd_528; /* 0x4100 */
+ uint32_t analog_pfd_528_set;
+ uint32_t analog_pfd_528_clr;
+ uint32_t analog_pfd_528_tog;
+};
+#endif
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_RBC_EN (1 << 27)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
+#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
+#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
+#define MXC_CCM_CCR_COSC_EN (1 << 12)
+#if (defined(CFG_MX6SL) || defined(CFG_MX6QP))
+#define MXC_CCM_CCR_OSCNT_MASK 0x7F
+#else
+#define MXC_CCM_CCR_OSCNT_MASK 0xFF
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET 0
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
+#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
+#ifdef CFG_MX6QP
+#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
+#endif
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSC_READY (1 << 5)
+#define MXC_CCM_CSR_REF_EN_B (1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
+#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
+#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
+#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
+#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
+#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
+#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL (1 << 8)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
+#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
+#endif
+#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
+#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
+#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
+#ifndef CFG_MX6SX
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
+#endif
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
+#ifndef CFG_MX6SX
+#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
+#endif
+#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
+#ifndef CFG_MX6SX
+#ifdef CFG_MX6QP
+#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
+#else
+#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
+#endif
+#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
+#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
+#endif
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
+#ifdef CFG_MX6SX
+#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
+#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
+#else
+#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
+#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
+#endif
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
+/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
+#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
+#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
+#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
+#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
+#if (defined(CFG_MX6SL) || defined(CFG_MX6SX) || defined(CFG_MX6QP))
+#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
+#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
+#endif
+#if (defined(CFG_MX6SL) || defined(CFG_MX6SX))
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
+#endif
+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
+
+/* Define the bits in register CSCMR2 */
+#ifdef CFG_MX6SX
+#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
+#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
+#endif
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
+#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
+#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
+#if (defined(CFG_MX6SX) || defined(CFG_MX6QP))
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
+#endif
+#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
+#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
+
+/* Define the bits in register CSCDR1 */
+#ifndef CFG_MX6SX
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
+#endif
+#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
+#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
+#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
+#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
+#ifndef CFG_MX6SX
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#endif
+#if (defined(CFG_MX6SL) || defined(CFG_MX6SX) || defined(CFG_MX6QP))
+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
+#endif
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
+
+/* Define the bits in register CS1CDR */
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
+#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
+
+/* Define the bits in register CS2CDR */
+#ifdef CFG_MX6SX
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
+#else
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
+
+#ifdef CFG_MX6QP
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 15
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x7) << 15)
+#else
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
+#endif
+#endif
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
+
+/* Define the bits in register CDCDR */
+#ifndef CFG_MX6SX
+#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
+#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
+#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
+#endif
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
+
+/* Define the bits in register CHSCCDR */
+#ifdef CFG_MX6SX
+#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
+#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
+#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
+#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
+#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
+#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
+#else
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
+#endif
+
+#define CHSCCDR_CLK_SEL_LDB_DI0 3
+#define CHSCCDR_PODF_DIVIDE_BY_3 2
+#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
+#ifdef CFG_MX6QP
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_OFFSET 18
+#endif
+
+/* All IPU2_DI1 are LCDIF1 on MX6SX */
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
+/* All IPU2_DI0 are LCDIF2 on MX6SX */
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
+#endif
+#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
+#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
+#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
+#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
+#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
+#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
+#endif
+#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
+#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
+#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
+#endif
+#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
+#define MXC_CCM_CLPCR_VSTBY (1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
+#define MXC_CCM_CLPCR_SBYOS (1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
+#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
+#endif
+#define MXC_CCM_CLPCR_LPM_MASK 0x3
+#define MXC_CCM_CLPCR_LPM_OFFSET 0
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
+#endif
+#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
+#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
+#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
+#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
+#define MXC_CCM_CISR_COSC_READY (1 << 6)
+#define MXC_CCM_CISR_LRF_PLL 1
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
+#endif
+#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
+#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
+#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
+#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
+#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
+#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
+#define MXC_CCM_CIMR_MASK_LRF_PLL 1
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
+#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
+#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
+#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
+#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGR_CG_MASK 3
+
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
+#define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
+#define MXC_CCM_CCGR0_ASRC_OFFSET 6
+#define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_OFFSET 14
+#define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_OFFSET 18
+#define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_OFFSET 24
+#define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_OFFSET 26
+#define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
+#define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
+#else
+#define MXC_CCM_CCGR0_DTCP_OFFSET 28
+#define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
+#endif
+
+#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
+#define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
+#define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
+#define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
+#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
+#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#endif
+#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
+#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
+#define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_OFFSET 16
+#define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
+#define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
+#endif
+#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
+#define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR1_GPU2D_OFFSET 24
+#define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
+#endif
+#define MXC_CCM_CCGR1_GPU3D_OFFSET 26
+#define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
+#define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
+#define MXC_CCM_CCGR1_CANFD_OFFSET 30
+#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
+#endif
+
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#else
+#define MXC_CCM_CCGR2_CSI_OFFSET 2
+#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
+#endif
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#endif
+#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
+#define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
+#define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
+#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR2_LCD_OFFSET 28
+#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
+#define MXC_CCM_CCGR2_PXP_OFFSET 30
+#define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
+#else
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+#endif
+
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR3_M4_OFFSET 2
+#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
+#define MXC_CCM_CCGR3_ENET_OFFSET 4
+#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
+#define MXC_CCM_CCGR3_QSPI_OFFSET 14
+#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
+#else
+#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#endif
+#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
+#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR3_QSPI1_OFFSET 14
+#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
+#else
+#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
+#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#endif
+#define MXC_CCM_CCGR3_MLB_OFFSET 18
+#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#endif
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
+#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+#endif
+
+#define MXC_CCM_CCGR4_PCIE_OFFSET 0
+#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
+#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
+#else
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#endif
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_OFFSET 16
+#define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_OFFSET 18
+#define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_OFFSET 20
+#define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_OFFSET 22
+#define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+
+#define MXC_CCM_CCGR5_ROM_OFFSET 0
+#define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
+#ifndef CFG_MX6SX
+#define MXC_CCM_CCGR5_SATA_OFFSET 4
+#define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
+#endif
+#define MXC_CCM_CCGR5_SDMA_OFFSET 6
+#define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_OFFSET 12
+#define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_OFFSET 14
+#define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_OFFSET 18
+#define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_OFFSET 20
+#define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_OFFSET 22
+#define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_UART_OFFSET 24
+#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR5_SAI1_OFFSET 20
+#define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
+#define MXC_CCM_CCGR5_SAI2_OFFSET 30
+#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
+#endif
+
+#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
+#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
+#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
+#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
+#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
+#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#ifdef CFG_MX6SX
+#define MXC_CCM_CCGR6_PWM8_OFFSET 16
+#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
+#define MXC_CCM_CCGR6_VADC_OFFSET 20
+#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
+#define MXC_CCM_CCGR6_GIS_OFFSET 22
+#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
+#define MXC_CCM_CCGR6_I2C4_OFFSET 24
+#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
+#define MXC_CCM_CCGR6_PWM5_OFFSET 26
+#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
+#define MXC_CCM_CCGR6_PWM6_OFFSET 28
+#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
+#define MXC_CCM_CCGR6_PWM7_OFFSET 30
+#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
+#else
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+#ifdef CFG_MX6QP
+#define MXC_CCM_CCGR6_VPUCLK_OFFSET 14
+#define MXC_CCM_CCGR6_VPUCLK_MASK (3 << MXC_CCM_CCGR6_VPUCLK_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK0_OFFSET 16
+#define MXC_CCM_CCGR6_PRE_CLK0_MASK (3 << MXC_CCM_CCGR6_PRE_CLK0_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK1_OFFSET 18
+#define MXC_CCM_CCGR6_PRE_CLK1_MASK (3 << MXC_CCM_CCGR6_PRE_CLK1_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK2_OFFSET 20
+#define MXC_CCM_CCGR6_PRE_CLK2_MASK (3 << MXC_CCM_CCGR6_PRE_CLK2_OFFSET)
+#define MXC_CCM_CCGR6_PRE_CLK3_OFFSET 22
+#define MXC_CCM_CCGR6_PRE_CLK3_MASK (3 << MXC_CCM_CCGR6_PRE_CLK3_OFFSET)
+#define MXC_CCM_CCGR6_PRG_CLK0_OFFSET 24
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
+#define MXC_CCM_CCGR6_PRG_CLK1_OFFSET 26
+#define MXC_CCM_CCGR6_PRG_CLK1_MASK (3 << MXC_CCM_CCGR6_PRG_CLK1_OFFSET)
+#endif
+#endif
+
+#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
+#define BP_ANADIG_PLL_SYS_RSVD0 20
+#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
+#define BF_ANADIG_PLL_SYS_RSVD0(v) \
+ (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
+#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
+#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
+#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
+#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
+#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
+#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
+#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
+ (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
+
+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
+#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
+#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
+ (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
+#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
+ (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
+#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
+ (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+
+#define BM_ANADIG_PLL_528_LOCK 0x80000000
+#define BP_ANADIG_PLL_528_RSVD1 19
+#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
+#define BF_ANADIG_PLL_528_RSVD1(v) \
+ (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
+#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_528_BYPASS 0x00010000
+#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_528_ENABLE 0x00002000
+#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_528_RSVD0 1
+#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
+#define BF_ANADIG_PLL_528_RSVD0(v) \
+ (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
+#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
+
+#define BP_ANADIG_PLL_528_SS_STOP 16
+#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
+#define BF_ANADIG_PLL_528_SS_STOP(v) \
+ (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
+#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
+#define BP_ANADIG_PLL_528_SS_STEP 0
+#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
+#define BF_ANADIG_PLL_528_SS_STEP(v) \
+ (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
+
+#define BP_ANADIG_PLL_528_NUM_RSVD0 30
+#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
+#define BP_ANADIG_PLL_528_NUM_A 0
+#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_NUM_A(v) \
+ (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
+
+#define BP_ANADIG_PLL_528_DENOM_RSVD0 30
+#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
+#define BP_ANADIG_PLL_528_DENOM_B 0
+#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_DENOM_B(v) \
+ (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
+
+#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
+#define BP_ANADIG_PLL_AUDIO_RSVD0 22
+#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
+#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
+ (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
+ (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
+ (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
+#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
+#define BP_ANADIG_PLL_AUDIO_NUM_A 0
+#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
+ (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
+
+#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
+#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
+#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
+ (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
+#define BP_ANADIG_PLL_VIDEO_RSVD0 22
+#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
+#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
+ (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
+ (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
+ (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
+#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
+#define BP_ANADIG_PLL_VIDEO_NUM_A 0
+#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
+ (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
+
+#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
+#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
+ (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
+#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
+ (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
+#define BP_ANADIG_PLL_ENET_RSVD1 21
+#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
+#define BF_ANADIG_PLL_ENET_RSVD1(v) \
+ (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
+#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
+ (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
+#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_ENET_RSVD0 2
+#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
+#define BF_ANADIG_PLL_ENET_RSVD0(v) \
+ (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
+ (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_480_PFD3_FRAC 24
+#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
+ (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
+#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_480_PFD2_FRAC 16
+#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
+ (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
+#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_480_PFD1_FRAC 8
+#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
+ (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
+#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_480_PFD0_FRAC 0
+#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
+ (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
+
+#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_528_PFD3_FRAC 24
+#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
+ (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
+#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_528_PFD2_FRAC 16
+#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
+ (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
+#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_528_PFD1_FRAC 8
+#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
+ (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
+#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_528_PFD0_FRAC 0
+#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
+ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
+
+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+
+#endif /*CCM_REGS_H */
diff --git a/core/arch/arm/plat-imx/imx-regs.h b/core/arch/arm/plat-imx/imx-regs.h
new file mode 100644
index 0000000..32baed5
--- /dev/null
+++ b/core/arch/arm/plat-imx/imx-regs.h
@@ -0,0 +1,917 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef IMX_REGS_H
+#define IMX_REGS_H
+
+#define ARCH_MXC
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define ROMCP_ARB_BASE_ADDR 0x00000000
+#define ROMCP_ARB_END_ADDR 0x000FFFFF
+
+#ifdef CFG_MX6SL
+#define GPU_2D_ARB_BASE_ADDR 0x02200000
+#define GPU_2D_ARB_END_ADDR 0x02203FFF
+#define OPENVG_ARB_BASE_ADDR 0x02204000
+#define OPENVG_ARB_END_ADDR 0x02207FFF
+#elifdef CFG_MX6SX
+#define CAAM_ARB_BASE_ADDR 0x00100000
+#define CAAM_ARB_END_ADDR 0x00107FFF
+#define GPU_ARB_BASE_ADDR 0x01800000
+#define GPU_ARB_END_ADDR 0x01803FFF
+#define APBH_DMA_ARB_BASE_ADDR 0x01804000
+#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
+#define M4_BOOTROM_BASE_ADDR 0x007F8000
+
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
+#else
+#define CAAM_ARB_BASE_ADDR 0x00100000
+#define CAAM_ARB_END_ADDR 0x00103FFF
+#define APBH_DMA_ARB_BASE_ADDR 0x00110000
+#define APBH_DMA_ARB_END_ADDR 0x00117FFF
+#define HDMI_ARB_BASE_ADDR 0x00120000
+#define HDMI_ARB_END_ADDR 0x00128FFF
+#define GPU_3D_ARB_BASE_ADDR 0x00130000
+#define GPU_3D_ARB_END_ADDR 0x00133FFF
+#define GPU_2D_ARB_BASE_ADDR 0x00134000
+#define GPU_2D_ARB_END_ADDR 0x00137FFF
+#define DTCP_ARB_BASE_ADDR 0x00138000
+#define DTCP_ARB_END_ADDR 0x0013BFFF
+#endif /* CFG_MX6SL */
+
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
+/* GPV - PL301 configuration ports */
+#if (defined(CFG_MX6SL) || defined(CFG_MX6SX))
+#define GPV2_BASE_ADDR 0x00D00000
+#else
+#define GPV2_BASE_ADDR 0x00200000
+#endif
+
+#ifdef CFG_MX6SX
+#define GPV3_BASE_ADDR 0x00E00000
+#define GPV4_BASE_ADDR 0x00F00000
+#define GPV5_BASE_ADDR 0x01000000
+#define GPV6_BASE_ADDR 0x01100000
+#define PCIE_ARB_BASE_ADDR 0x08000000
+#define PCIE_ARB_END_ADDR 0x08FFFFFF
+
+#else
+#define GPV3_BASE_ADDR 0x00300000
+#define GPV4_BASE_ADDR 0x00800000
+#define PCIE_ARB_BASE_ADDR 0x01000000
+#define PCIE_ARB_END_ADDR 0x01FFFFFF
+#endif
+
+#define IRAM_BASE_ADDR 0x00900000
+#define SCU_BASE_ADDR 0x00A00000
+#define IC_INTERFACES_BASE_ADDR 0x00A00100
+#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
+#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
+#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
+#define L2_PL310_BASE 0x00A02000
+#define GPV0_BASE_ADDR 0x00B00000
+#define GPV1_BASE_ADDR 0x00C00000
+
+#define AIPS1_ARB_BASE_ADDR 0x02000000
+#define AIPS1_ARB_END_ADDR 0x020FFFFF
+#define AIPS2_ARB_BASE_ADDR 0x02100000
+#define AIPS2_ARB_END_ADDR 0x021FFFFF
+#ifdef CFG_MX6SX
+#define AIPS3_ARB_BASE_ADDR 0x02200000
+#define AIPS3_ARB_END_ADDR 0x022FFFFF
+#define WEIM_ARB_BASE_ADDR 0x50000000
+#define WEIM_ARB_END_ADDR 0x57FFFFFF
+#define QSPI0_AMBA_BASE 0x60000000
+#define QSPI0_AMBA_END 0x6FFFFFFF
+#define QSPI1_AMBA_BASE 0x70000000
+#define QSPI1_AMBA_END 0x7FFFFFFF
+#else
+#define SATA_ARB_BASE_ADDR 0x02200000
+#define SATA_ARB_END_ADDR 0x02203FFF
+#define OPENVG_ARB_BASE_ADDR 0x02204000
+#define OPENVG_ARB_END_ADDR 0x02207FFF
+#define HSI_ARB_BASE_ADDR 0x02208000
+#define HSI_ARB_END_ADDR 0x0220BFFF
+#define IPU1_ARB_BASE_ADDR 0x02400000
+#define IPU1_ARB_END_ADDR 0x027FFFFF
+#define IPU2_ARB_BASE_ADDR 0x02800000
+#define IPU2_ARB_END_ADDR 0x02BFFFFF
+#define WEIM_ARB_BASE_ADDR 0x08000000
+#define WEIM_ARB_END_ADDR 0x0FFFFFFF
+#endif
+
+#if (defined(CFG_MX6SL) || defined(CFG_MX6SX))
+#define MMDC0_ARB_BASE_ADDR 0x80000000
+#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
+#define MMDC1_ARB_BASE_ADDR 0xC0000000
+#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+#else
+#define MMDC0_ARB_BASE_ADDR 0x10000000
+#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
+#define MMDC1_ARB_BASE_ADDR 0x80000000
+#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+#endif
+
+#ifndef CFG_MX6SX
+#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
+#define IPU_SOC_OFFSET 0x00200000
+#endif
+
+/* Defines for Blocks connected via AIPS (SkyBlue) */
+#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
+#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
+#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
+#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
+
+#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
+#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
+#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
+#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
+#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
+#ifdef CFG_MX6SL
+#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
+#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
+#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
+#else
+#ifndef CFG_MX6SX
+#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#endif
+/* #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) */
+#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
+#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#endif
+
+#ifndef CFG_MX6SX
+#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
+#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
+#endif
+#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
+
+#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
+#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
+#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
+#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
+#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
+#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
+#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
+#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
+#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
+#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
+#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
+#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
+#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
+#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
+#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
+#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
+#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
+#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
+#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
+#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
+#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
+#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
+#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
+#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
+#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
+#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
+#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
+#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
+#ifdef CFG_MX6SL
+#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#elifdef CFG_MX6SX
+#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
+#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
+#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
+#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
+#else
+#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#endif
+
+#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
+#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
+#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
+#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
+
+#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
+#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
+
+#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
+
+#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
+#ifdef CFG_MX6SL
+#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+#else
+#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+#endif
+
+#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
+#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
+#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
+#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
+#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
+#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
+#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
+#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
+#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
+#ifdef CFG_MX6SL
+#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#elifdef CFG_MX6SX
+#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#else
+#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#endif
+
+#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
+#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
+#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
+#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#ifdef CFG_MX6SX
+#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#else
+#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#endif
+#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
+#ifdef CFG_MX6SX
+#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
+#else
+#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
+#endif
+#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
+#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
+#ifdef CFG_MX6SX
+#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#else
+#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#endif
+/* #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) */
+#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
+#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
+#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
+
+#ifdef CFG_MX6SX
+#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
+#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
+#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
+#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
+#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
+#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
+#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
+#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
+#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
+#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
+#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
+#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
+#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
+#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
+#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
+#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
+#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
+#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
+#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
+#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
+#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
+#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
+#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
+#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
+#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
+#endif
+
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_2 0x12
+#define CHIP_REV_1_5 0x15
+#define CHIP_REV_2_0 0x20
+#ifndef CFG_MX6SX
+#define IRAM_SIZE 0x00040000
+#else
+#define IRAM_SIZE 0x00020000
+#endif
+#define FEC_QUIRK_ENET_MAC
+
+#ifndef __ASSEMBLY__
+#include <stdint.h>
+
+extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
+#define SRC_SCR_CORE_1_RESET_OFFSET 14
+#define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
+#define SRC_SCR_CORE_2_RESET_OFFSET 15
+#define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
+#define SRC_SCR_CORE_3_RESET_OFFSET 16
+#define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
+#define SRC_SCR_CORE_1_ENABLE_OFFSET 22
+#define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
+#define SRC_SCR_CORE_2_ENABLE_OFFSET 23
+#define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
+#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
+#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
+
+/* WEIM registers */
+struct weim {
+ uint32_t cs0gcr1;
+ uint32_t cs0gcr2;
+ uint32_t cs0rcr1;
+ uint32_t cs0rcr2;
+ uint32_t cs0wcr1;
+ uint32_t cs0wcr2;
+
+ uint32_t cs1gcr1;
+ uint32_t cs1gcr2;
+ uint32_t cs1rcr1;
+ uint32_t cs1rcr2;
+ uint32_t cs1wcr1;
+ uint32_t cs1wcr2;
+
+ uint32_t cs2gcr1;
+ uint32_t cs2gcr2;
+ uint32_t cs2rcr1;
+ uint32_t cs2rcr2;
+ uint32_t cs2wcr1;
+ uint32_t cs2wcr2;
+
+ uint32_t cs3gcr1;
+ uint32_t cs3gcr2;
+ uint32_t cs3rcr1;
+ uint32_t cs3rcr2;
+ uint32_t cs3wcr1;
+ uint32_t cs3wcr2;
+
+ uint32_t unused[12];
+
+ uint32_t wcr;
+ uint32_t wiar;
+ uint32_t ear;
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+ uint32_t scr;
+ uint32_t sbmr1;
+ uint32_t srsr;
+ uint32_t reserved1[2];
+ uint32_t sisr;
+ uint32_t simr;
+ uint32_t sbmr2;
+ uint32_t gpr1;
+ uint32_t gpr2;
+ uint32_t gpr3;
+ uint32_t gpr4;
+ uint32_t gpr5;
+ uint32_t gpr6;
+ uint32_t gpr7;
+ uint32_t gpr8;
+ uint32_t gpr9;
+ uint32_t gpr10;
+};
+
+struct snvs_regs {
+ uint32_t hplr; /* 0x00 */
+ uint32_t hpcomr; /* 0x04 */
+ uint32_t hpcr; /* 0x08 */
+ uint32_t spare1; /* 0x0c */
+ uint32_t spare2; /* 0x10 */
+ uint32_t hpsr; /* 0x14 */
+ uint32_t spare3; /* 0x18 */
+ uint32_t spare4; /* 0x1c */
+ uint32_t spare5; /* 0x20 */
+ uint32_t hprtcmr; /* 0x24 */
+ uint32_t hprtclr; /* 0x28 */
+ uint32_t hptamr; /* 0x2c */
+ uint32_t hptalr; /* 0x30 */
+ uint32_t lplr; /* 0x34 */
+ uint32_t lpcr; /* 0x38 */
+ uint32_t spare6; /* 0x3c */
+ uint32_t spare7; /* 0x40 */
+ uint32_t spare8; /* 0x44 */
+ uint32_t spare9; /* 0x48 */
+ uint32_t lpsr; /* 0x4c */
+ uint32_t spare10; /* 0x50 */
+ uint32_t spare11; /* 0x54 */
+ uint32_t spare12; /* 0x58 */
+ uint32_t lpsmcmr; /* 0x5c */
+ uint32_t lpsmclr; /* 0x60 */
+ uint32_t spare13; /* 0x64 */
+ uint32_t lpgpr; /* 0x68 */
+ uint8_t spare_block[0xbf8 - 0x6c]; /* 0x6c */
+ uint32_t hpvidr1; /* 0xbf8 */
+ uint32_t hpvidr2; /* 0xbfc */
+};
+
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
+#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
+
+/* GPR3 bitfields */
+#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
+#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
+#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
+#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
+#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
+
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
+
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
+#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
+#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+
+
+struct iomuxc {
+#ifdef CFG_MX6SX
+ uint8_t reserved[0x4000];
+#endif
+ uint32_t gpr[14];
+};
+
+struct gpc {
+ uint32_t cntr;
+ uint32_t pgr;
+ uint32_t imr1;
+ uint32_t imr2;
+ uint32_t imr3;
+ uint32_t imr4;
+ uint32_t isr1;
+ uint32_t isr2;
+ uint32_t isr3;
+ uint32_t isr4;
+};
+
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
+
+#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
+#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
+#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
+
+#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
+#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
+#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_BITMAP_SPWG 0
+#define IOMUXC_GPR2_BITMAP_JEIDA 1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18 0
+#define IOMUXC_GPR2_DATA_WIDTH_24 1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
+#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED 0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
+
+#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
+#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
+/* ECSPI registers */
+struct cspi_regs {
+ uint32_t rxdata;
+ uint32_t txdata;
+ uint32_t ctrl;
+ uint32_t cfg;
+ uint32_t intr;
+ uint32_t dma;
+ uint32_t stat;
+ uint32_t period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN (1 << 0)
+#define MXC_CSPICTRL_MODE (1 << 1)
+#define MXC_CSPICTRL_XCH (1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPICTRL_TC (1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+#define MAX_SPI_BYTES 32
+#define SPI_MAX_NUM 4
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN 18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
+#if defined(CFG_MX6SL) || defined(CFG_MX6DL)
+#define MXC_SPI_BASE_ADDRESSES \
+ ECSPI1_BASE_ADDR, \
+ ECSPI2_BASE_ADDR, \
+ ECSPI3_BASE_ADDR, \
+ ECSPI4_BASE_ADDR
+#else
+#define MXC_SPI_BASE_ADDRESSES \
+ ECSPI1_BASE_ADDR, \
+ ECSPI2_BASE_ADDR, \
+ ECSPI3_BASE_ADDR, \
+ ECSPI4_BASE_ADDR, \
+ ECSPI5_BASE_ADDR
+#endif
+
+struct ocotp_regs {
+ uint32_t ctrl;
+ uint32_t ctrl_set;
+ uint32_t ctrl_clr;
+ uint32_t ctrl_tog;
+ uint32_t timing;
+ uint32_t rsvd0[3];
+ uint32_t data;
+ uint32_t rsvd1[3];
+ uint32_t read_ctrl;
+ uint32_t rsvd2[3];
+ uint32_t read_fuse_data;
+ uint32_t rsvd3[3];
+ uint32_t sw_sticky;
+ uint32_t rsvd4[3];
+ uint32_t scs;
+ uint32_t scs_set;
+ uint32_t scs_clr;
+ uint32_t scs_tog;
+ uint32_t crc_addr;
+ uint32_t rsvd5[3];
+ uint32_t crc_value;
+ uint32_t rsvd6[3];
+ uint32_t version;
+ uint32_t rsvd7[0xdb];
+
+ struct fuse_bank {
+ uint32_t fuse_regs[0x20];
+ } bank[16];
+};
+
+struct fuse_bank0_regs {
+ uint32_t lock;
+ uint32_t rsvd0[3];
+ uint32_t uid_low;
+ uint32_t rsvd1[3];
+ uint32_t uid_high;
+ uint32_t rsvd2[3];
+ uint32_t cfg2;
+ uint32_t rsvd3[3];
+ uint32_t cfg3;
+ uint32_t rsvd4[3];
+ uint32_t cfg4;
+ uint32_t rsvd5[3];
+ uint32_t cfg5;
+ uint32_t rsvd6[3];
+ uint32_t cfg6;
+ uint32_t rsvd7[3];
+};
+
+struct fuse_bank1_regs {
+ uint32_t mem0;
+ uint32_t rsvd0[3];
+ uint32_t mem1;
+ uint32_t rsvd1[3];
+ uint32_t mem2;
+ uint32_t rsvd2[3];
+ uint32_t mem3;
+ uint32_t rsvd3[3];
+ uint32_t mem4;
+ uint32_t rsvd4[3];
+ uint32_t ana0;
+ uint32_t rsvd5[3];
+ uint32_t ana1;
+ uint32_t rsvd6[3];
+ uint32_t ana2;
+ uint32_t rsvd7[3];
+};
+
+#ifdef CFG_MX6SX
+struct fuse_bank4_regs {
+ uint32_t sjc_resp_low;
+ uint32_t rsvd0[3];
+ uint32_t sjc_resp_high;
+ uint32_t rsvd1[3];
+ uint32_t mac_addr_low;
+ uint32_t rsvd2[3];
+ uint32_t mac_addr_high;
+ uint32_t rsvd3[3];
+ uint32_t mac_addr2;
+ uint32_t rsvd4[7];
+ uint32_t gp1;
+ uint32_t rsvd5[7];
+};
+#else
+struct fuse_bank4_regs {
+ uint32_t sjc_resp_low;
+ uint32_t rsvd0[3];
+ uint32_t sjc_resp_high;
+ uint32_t rsvd1[3];
+ uint32_t mac_addr_low;
+ uint32_t rsvd2[3];
+ uint32_t mac_addr_high;
+ uint32_t rsvd3[0xb];
+ uint32_t gp1;
+ uint32_t rsvd4[3];
+ uint32_t gp2;
+ uint32_t rsvd5[3];
+};
+#endif
+
+struct aipstz_regs {
+ uint32_t mprot0;
+ uint32_t mprot1;
+ uint32_t rsvd[0xe];
+ uint32_t opacr0;
+ uint32_t opacr1;
+ uint32_t opacr2;
+ uint32_t opacr3;
+ uint32_t opacr4;
+};
+
+struct anatop_regs {
+ uint32_t pll_sys; /* 0x000 */
+ uint32_t pll_sys_set; /* 0x004 */
+ uint32_t pll_sys_clr; /* 0x008 */
+ uint32_t pll_sys_tog; /* 0x00c */
+ uint32_t usb1_pll_480_ctrl; /* 0x010 */
+ uint32_t usb1_pll_480_ctrl_set; /* 0x014 */
+ uint32_t usb1_pll_480_ctrl_clr; /* 0x018 */
+ uint32_t usb1_pll_480_ctrl_tog; /* 0x01c */
+ uint32_t usb2_pll_480_ctrl; /* 0x020 */
+ uint32_t usb2_pll_480_ctrl_set; /* 0x024 */
+ uint32_t usb2_pll_480_ctrl_clr; /* 0x028 */
+ uint32_t usb2_pll_480_ctrl_tog; /* 0x02c */
+ uint32_t pll_528; /* 0x030 */
+ uint32_t pll_528_set; /* 0x034 */
+ uint32_t pll_528_clr; /* 0x038 */
+ uint32_t pll_528_tog; /* 0x03c */
+ uint32_t pll_528_ss; /* 0x040 */
+ uint32_t rsvd0[3];
+ uint32_t pll_528_num; /* 0x050 */
+ uint32_t rsvd1[3];
+ uint32_t pll_528_denom; /* 0x060 */
+ uint32_t rsvd2[3];
+ uint32_t pll_audio; /* 0x070 */
+ uint32_t pll_audio_set; /* 0x074 */
+ uint32_t pll_audio_clr; /* 0x078 */
+ uint32_t pll_audio_tog; /* 0x07c */
+ uint32_t pll_audio_num; /* 0x080 */
+ uint32_t rsvd3[3];
+ uint32_t pll_audio_denom; /* 0x090 */
+ uint32_t rsvd4[3];
+ uint32_t pll_video; /* 0x0a0 */
+ uint32_t pll_video_set; /* 0x0a4 */
+ uint32_t pll_video_clr; /* 0x0a8 */
+ uint32_t pll_video_tog; /* 0x0ac */
+ uint32_t pll_video_num; /* 0x0b0 */
+ uint32_t rsvd5[3];
+ uint32_t pll_video_denom; /* 0x0c0 */
+ uint32_t rsvd6[3];
+ uint32_t pll_mlb; /* 0x0d0 */
+ uint32_t pll_mlb_set; /* 0x0d4 */
+ uint32_t pll_mlb_clr; /* 0x0d8 */
+ uint32_t pll_mlb_tog; /* 0x0dc */
+ uint32_t pll_enet; /* 0x0e0 */
+ uint32_t pll_enet_set; /* 0x0e4 */
+ uint32_t pll_enet_clr; /* 0x0e8 */
+ uint32_t pll_enet_tog; /* 0x0ec */
+ uint32_t pfd_480; /* 0x0f0 */
+ uint32_t pfd_480_set; /* 0x0f4 */
+ uint32_t pfd_480_clr; /* 0x0f8 */
+ uint32_t pfd_480_tog; /* 0x0fc */
+ uint32_t pfd_528; /* 0x100 */
+ uint32_t pfd_528_set; /* 0x104 */
+ uint32_t pfd_528_clr; /* 0x108 */
+ uint32_t pfd_528_tog; /* 0x10c */
+ uint32_t reg_1p1; /* 0x110 */
+ uint32_t reg_1p1_set; /* 0x114 */
+ uint32_t reg_1p1_clr; /* 0x118 */
+ uint32_t reg_1p1_tog; /* 0x11c */
+ uint32_t reg_3p0; /* 0x120 */
+ uint32_t reg_3p0_set; /* 0x124 */
+ uint32_t reg_3p0_clr; /* 0x128 */
+ uint32_t reg_3p0_tog; /* 0x12c */
+ uint32_t reg_2p5; /* 0x130 */
+ uint32_t reg_2p5_set; /* 0x134 */
+ uint32_t reg_2p5_clr; /* 0x138 */
+ uint32_t reg_2p5_tog; /* 0x13c */
+ uint32_t reg_core; /* 0x140 */
+ uint32_t reg_core_set; /* 0x144 */
+ uint32_t reg_core_clr; /* 0x148 */
+ uint32_t reg_core_tog; /* 0x14c */
+ uint32_t ana_misc0; /* 0x150 */
+ uint32_t ana_misc0_set; /* 0x154 */
+ uint32_t ana_misc0_clr; /* 0x158 */
+ uint32_t ana_misc0_tog; /* 0x15c */
+ uint32_t ana_misc1; /* 0x160 */
+ uint32_t ana_misc1_set; /* 0x164 */
+ uint32_t ana_misc1_clr; /* 0x168 */
+ uint32_t ana_misc1_tog; /* 0x16c */
+ uint32_t ana_misc2; /* 0x170 */
+ uint32_t ana_misc2_set; /* 0x174 */
+ uint32_t ana_misc2_clr; /* 0x178 */
+ uint32_t ana_misc2_tog; /* 0x17c */
+ uint32_t tempsense0; /* 0x180 */
+ uint32_t tempsense0_set; /* 0x184 */
+ uint32_t tempsense0_clr; /* 0x188 */
+ uint32_t tempsense0_tog; /* 0x18c */
+ uint32_t tempsense1; /* 0x190 */
+ uint32_t tempsense1_set; /* 0x194 */
+ uint32_t tempsense1_clr; /* 0x198 */
+ uint32_t tempsense1_tog; /* 0x19c */
+ uint32_t usb1_vbus_detect; /* 0x1a0 */
+ uint32_t usb1_vbus_detect_set; /* 0x1a4 */
+ uint32_t usb1_vbus_detect_clr; /* 0x1a8 */
+ uint32_t usb1_vbus_detect_tog; /* 0x1ac */
+ uint32_t usb1_chrg_detect; /* 0x1b0 */
+ uint32_t usb1_chrg_detect_set; /* 0x1b4 */
+ uint32_t usb1_chrg_detect_clr; /* 0x1b8 */
+ uint32_t usb1_chrg_detect_tog; /* 0x1bc */
+ uint32_t usb1_vbus_det_stat; /* 0x1c0 */
+ uint32_t usb1_vbus_det_stat_set; /* 0x1c4 */
+ uint32_t usb1_vbus_det_stat_clr; /* 0x1c8 */
+ uint32_t usb1_vbus_det_stat_tog; /* 0x1cc */
+ uint32_t usb1_chrg_det_stat; /* 0x1d0 */
+ uint32_t usb1_chrg_det_stat_set; /* 0x1d4 */
+ uint32_t usb1_chrg_det_stat_clr; /* 0x1d8 */
+ uint32_t usb1_chrg_det_stat_tog; /* 0x1dc */
+ uint32_t usb1_loopback; /* 0x1e0 */
+ uint32_t usb1_loopback_set; /* 0x1e4 */
+ uint32_t usb1_loopback_clr; /* 0x1e8 */
+ uint32_t usb1_loopback_tog; /* 0x1ec */
+ uint32_t usb1_misc; /* 0x1f0 */
+ uint32_t usb1_misc_set; /* 0x1f4 */
+ uint32_t usb1_misc_clr; /* 0x1f8 */
+ uint32_t usb1_misc_tog; /* 0x1fc */
+ uint32_t usb2_vbus_detect; /* 0x200 */
+ uint32_t usb2_vbus_detect_set; /* 0x204 */
+ uint32_t usb2_vbus_detect_clr; /* 0x208 */
+ uint32_t usb2_vbus_detect_tog; /* 0x20c */
+ uint32_t usb2_chrg_detect; /* 0x210 */
+ uint32_t usb2_chrg_detect_set; /* 0x214 */
+ uint32_t usb2_chrg_detect_clr; /* 0x218 */
+ uint32_t usb2_chrg_detect_tog; /* 0x21c */
+ uint32_t usb2_vbus_det_stat; /* 0x220 */
+ uint32_t usb2_vbus_det_stat_set; /* 0x224 */
+ uint32_t usb2_vbus_det_stat_clr; /* 0x228 */
+ uint32_t usb2_vbus_det_stat_tog; /* 0x22c */
+ uint32_t usb2_chrg_det_stat; /* 0x230 */
+ uint32_t usb2_chrg_det_stat_set; /* 0x234 */
+ uint32_t usb2_chrg_det_stat_clr; /* 0x238 */
+ uint32_t usb2_chrg_det_stat_tog; /* 0x23c */
+ uint32_t usb2_loopback; /* 0x240 */
+ uint32_t usb2_loopback_set; /* 0x244 */
+ uint32_t usb2_loopback_clr; /* 0x248 */
+ uint32_t usb2_loopback_tog; /* 0x24c */
+ uint32_t usb2_misc; /* 0x250 */
+ uint32_t usb2_misc_set; /* 0x254 */
+ uint32_t usb2_misc_clr; /* 0x258 */
+ uint32_t usb2_misc_tog; /* 0x25c */
+ uint32_t digprog; /* 0x260 */
+ uint32_t reserved1[7];
+ uint32_t digprog_sololite; /* 0x280 */
+};
+
+#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
+#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
+#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
+#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
+#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
+#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
+
+struct wdog_regs {
+ uint16_t wcr; /* Control */
+ uint16_t wsr; /* Service */
+ uint16_t wrsr; /* Reset Status */
+ uint16_t wicr; /* Interrupt Control */
+ uint16_t wmcr; /* Miscellaneous Control */
+};
+
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
+struct pwm_regs {
+ uint32_t cr;
+ uint32_t sr;
+ uint32_t ir;
+ uint32_t sar;
+ uint32_t pr;
+ uint32_t cnr;
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* IMX_REGS_H */
diff --git a/core/arch/arm/plat-imx/sub.mk b/core/arch/arm/plat-imx/sub.mk
index d0a2f51..42a1a2d 100644
--- a/core/arch/arm/plat-imx/sub.mk
+++ b/core/arch/arm/plat-imx/sub.mk
@@ -3,6 +3,7 @@ srcs-y += main.c
srcs-$(CFG_PL310) += imx_pl310.c
srcs-$(CFG_PSCI_ARM32) += psci.c
+srcs-$(CFG_FSL_CAAM) += clock.c caam_cmds.c
srcs-$(PLATFORM_FLAVOR_mx6qsabrelite) += a9_plat_init.S
srcs-$(PLATFORM_FLAVOR_mx6qsabresd) += a9_plat_init.S
diff --git a/core/drivers/crypto/desc.h b/core/drivers/crypto/desc.h
new file mode 100644
index 0000000..18e2ec8
--- /dev/null
+++ b/core/drivers/crypto/desc.h
@@ -0,0 +1,666 @@
+/*
+ * CAAM descriptor composition header
+ * Definitions to support CAAM descriptor instruction generation
+ *
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on desc.h file in linux drivers/crypto/caam
+ */
+
+#ifndef DESC_H
+#define DESC_H
+
+#define KEY_BLOB_SIZE 32
+#define MAC_SIZE 16