Sam and Noah

test.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 06/14/2018 03:56:38 PM
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
        input wire sw,
        output wire toggleout,
        
        input wire clk,
        input wire reset
    );
    
    reg [26:0] count1 = 27'b0;
    reg toggle = 1'b0;
    
    always @ (posedge clk or posedge reset)
    begin
      if(reset)
      begin
        count1 <= 0;      
      end
      else 
      begin 
      
        if(count1 >= 50000000)
        begin
          count1 <= count1 - 50000000;
        end
        
        else
        begin
          count1 <= count1 + sw;      
        end
                  
        if(toggle == 0)
        begin
          toggle <= 1;
        end
        else
        begin
          toggle <= 0;
        end
        
      end
    end
    assign toggleout = toggle;
endmodule

This is a synthesizable module but is not complete since I couldn't see the rest of your code. Glad to meet you and don't hesitate to ask questions.