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ScienceElectronicsFun/master-xdc.xdc

Created November 7, 2021 16:20
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Constraints file for Spartan 7 verilog CPU
Raw
master-xdc.xdc
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets klock_IBUF]
set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { klock }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVCMOS33 } [get_ports { reset }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
## port_out_00
set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports { port_out_00[0] }]; #IO_L4N_T0_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { port_out_00[1] }]; #IO_L4P_T0_35 Sch=btn[1]
set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports { port_out_00[2] }]; #IO_L4N_T0_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { port_out_00[3] }]; #IO_L4P_T0_35 Sch=btn[1]
set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { port_out_00[4] }]; #IO_L4N_T0_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { port_out_00[5] }]; #IO_L4P_T0_35 Sch=btn[1]
set_property -dict { PACKAGE_PIN U6 IOSTANDARD LVCMOS33 } [get_ports { port_out_00[6] }]; #IO_L4N_T0_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { port_out_00[7] }]; #IO_L4P_T0_35 Sch=btn[1]
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