MOD 8 Down Counter

MOD_8_Down.v

/**************DataPath*****************/
module Path(Out, clk);
input clk;
output [2:0]Out;
wire D, Q, Dn;
D D1(Qb, Q, Qb, clk);
D D2(Qb2, Q2, Qb2, Q);
D D3(Qb3, Q3, Qb3, Q2);
assign Out = {Qb3,Qb2,Qb};
endmodule


/************D_FF***************/
module D(Di,Q, Qb, clk);
input Di, clk;
output reg Q, Qb;
initial begin
Q = 1;
Qb = ~Q;
end
always @(negedge clk)begin
Qb <= ~Di;
Q <= Di;
end
endmodule