RTL_I2C_Master.v

module Master(clk, sda, scl);
input clk;
inout [0:0] sda;
output reg scl;

reg [7:0]register_address = 8'b10101011;
reg scl_flag;
reg [6:0] slave_address;
wire start_flag;
reg status;
reg direction;
reg sda_val;
reg scl_c;
reg [7:0]add_Read;
reg [4:0]count;
reg [6:0]slave_add_reserve;
reg acknowledgement=0;
reg [7:0]slave_data;
reg A;
reg B;


initial begin
count = 4'b0000;
scl = 1;
scl_flag = 0;
slave_address = 7'b1001101;
slave_add_reserve = 7'b1001101;
add_Read = {slave_address,1'b1};
direction = 1;
sda_val = 1;
#8 sda_val = 0;
A = 1;
B = 0;
end

//START CONDITION//

always @(negedge sda)begin
	if(scl == 1)
		A = 1;
end

//STOP CONDITION//*

always @(posedge sda)begin
	if(scl==1)begin
		B = 1;
	end
end	

assign #1 start_flag = A^B;
//CLOCKING SCL AFTER START BIT //
always @(posedge clk)begin
	if(start_flag==1)
		scl <= ~scl;
	else
		scl <= 1'b1;
end

// DATA TRANSFER //
always @(negedge clk)begin
	if(scl==0 && start_flag==1)begin
		count = count + 1;
		if(count<9)begin
			sda_val = add_Read[7];
			add_Read = add_Read << 1;
		end
		else if(count == 9)begin
			direction = 0;
		end
		else if(count >= 10 && count <18)begin
			direction = 1;
			if(count==10)begin
				acknowledgement = sda; //Storing SDA value in acknowledgement as SDA will continuously change
			end
			if(acknowledgement == 1)begin
				sda_val = register_address[7];
				register_address = register_address << 1;
			end
			else begin 
				count = 1;
				add_Read = {slave_add_reserve,1'b1};
				direction = 1;
				sda_val = add_Read[7];
				add_Read = add_Read << 1;
			end
		end
		else if(count == 18)begin
			direction = 0;
			acknowledgement = sda;
		end
	  else if(count > 18 && count<27)begin
			slave_data[0] = sda;
				slave_data = slave_data << 1; 

	  end
	  else if(count == 27)begin
			direction = 1;
			sda_val = 1; /*This is acknowledgement*/
		end
	  else begin
			sda_val = 0;
			direction = 1;
			status = 1;
		end
	end
	else if(scl == 1 && status == 1)begin
			sda_val = 1;
	end
end



assign sda = direction?sda_val:1'bZ;

Slave Slv(scl,sda);
endmodule