JK_FF_Test.v

module TestJK;







 // Inputs


 reg J;

 reg K;

 reg clk;

 // Outputs

 wire Q;

 wire Qbar;







 // Instantiate the Unit Under Test (UUT)


 initial begin

 // Initialize Inputs

 J = 0;

 K = 0;

 fork

 #4 K = 1;

 #12 J = 1;

 #12 K = 0;

 #20 J = 1;

 #20 K = 1;

 #46 J = 0;

 #46 K = 0;

 #54 K = 1;

 #62 J = 1;

 #62 K = 0;

 #70 K = 1;

 clk = 0;

 join

 // Wait 100 ns for global reset to finish

 #100;

        end







JKFF master(J,K,clk,Q,Qbar);








always #4 clk=!clk;


     

endmodule

JK_FlipFlop.v

module JKFF(j,k,c,q,qb);

input j,k,c;

output q,qb;

wire o;

and #1 (m,j,qb);

and #1 (n,!k,q);

or (o,m,n);

assign q = o;

assign qb = !q;

endmodule